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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper
users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem
add the new node into the work list because there is a potential for further optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Add a xform to the DAG combiner.Bill Wendling
Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Fortify r152675 a bit. Although I'm not able to come up with a test case ↵Evan Cheng
that would trigger the truncation case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Give dagcombiner's worklist some inline capacity.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng
performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson
providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy
converted to zeroexts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Remove extraneous #include and spelling mistake introduced in r150669.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy
N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem
extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15DAGCombiner: Deduplicate code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng
overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Teach the X86 instruction selection to do some heroic transforms toChandler Carruth
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper
subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Prevent a DAGCombine from firing where there are two uses ofChandler Carruth
a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-26Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman
location. PR10747, part 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth
undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this ↵Eli Friedman
doesn't affect any in-tree target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves ↵Eli Friedman
correctly. PR11494. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.Evan Cheng
Conservatively returns zero when the GV does not specify an alignment nor is it initialized. Previously it returns ABI alignment for type of the GV. However, if the type is a "packed" type, then the under-specified alignments is attached to the load / store instructions. In that case, the alignment of the type cannot be trusted. rdar://10464621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28DAG combine should not increase alignment of loads / stores with alignment lessEvan Cheng
than ABI alignment. These are loads / stores from / to "packed" data structures. Their alignments are intentionally under-specified. rdar://10301431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman
LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman
runs. Fixes PR11029. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames
Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV()Richard Osborne
and TargetLowering::BuildUDIV(). Fixes PR11283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31Cleanup. Document. Make sure that this build_vector optimization only runs ↵Nadav Rotem
before the op legalizer and that the used type is legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30Silence compiler warning.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-29Add a new DAGCombine optimization for BUILD_VECTOR.Nadav Rotem
If all of the inputs are zero/any_extended, create a new simple BV which can be further optimized by other BV optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27Don't crash on 128-bit sdiv by constant. Found by inspection.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25Remove a couple redundant checks.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman
worklist, as it may be possible to perform further optimization on them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes
subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman
same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Add codegen support for vector select (in the IR this means a selectDuncan Sands
with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Roll back the rest of r126557. It's a hack that will break in some obscure ↵Benjamin Kramer
cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Revert r137310 because it does not optimize any code on ToTNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137466 91177308-0d34-0410-b5e6-96231b3b80d8
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