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path: root/lib/CodeGen/PeepholeOptimizer.cpp
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2012-12-17Add debug prints for when optimizeLoadInstr folds a load.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Add comment for load foldingJoel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Make sure we iterate over newly created instructions. Fixes pr13625. Testcase toRafael Espindola
follow in one sec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Use standard pattern for iterate+erase.Jakob Stoklund Olesen
Increment the MBB iterator at the top of the loop to properly handle the current (and previous) instructions getting erased. This fixes PR13625. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen
Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren
instructions with two register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen
The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Style: Don't reuse variables for multiple purposes.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Revert r157755.Manman Ren
The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31X86: replace SUB with CMP if possibleManman Ren
This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20Constrain regclasses in PeepholeOptimizer.Jakob Stoklund Olesen
It can be necessary to restrict to a sub-class before accessing sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren
This commit broke an external linux bot and gave a compile-time warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01Tidy up. Naming conventions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25Make the peephole optimizer clear kill flags on a vreg if it's about to add newLang Hames
uses of the vreg, since the old kills may no longer be valid. This was causing -verify-machineinstrs to complain about uses after kills, and could potentially have been causing subtle register allocation issues, but I haven't come across a test case yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25Fixed typo.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Codegen pass definition cleanup. No functionality.Andrew Trick
Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13If MI is deleted then remove it from the set. If a new MI is created, it couldNick Lewycky
have the same address as the one we deleted, and we don't want that in the set yet. Noticed by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26SrcDef is only written and never read. Remove it.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15Add a peephole optimization to optimize pairs of bitcasts. e.g.Evan Cheng
v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15Fix thinko. Cmp can be the first instruction in a MBB.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Fix PR8854. Track inserted copies to avoid read before write. Sorry, it's ↵Evan Cheng
hard to reduce a sensible small test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07DBG_VALUE does not have any side effects; it also makes no sense to mark it ↵Evan Cheng
cheap as a copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Code clean up. The peephole pass should be the one updating the instructionEvan Cheng
iterator, not TII->OptimizeCompareInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling
at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01The testcase is now XFAILed. Sorry about the breakage.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Revert r117876 for now, it's causing more testsuite failures.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling
looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson
exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18Don't recompute MachineRegisterInfo in the Optimize* method.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12Begin adding static dependence information to passes, which will allow us toOwen Anderson
perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07Now with fewer extraneous semicolons!Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21Move the search for the appropriate AND instructionGabor Greif
into OptimizeCompareInstr. This necessitates the passing of CmpValue around, so widen the virtual functions to accomodate. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14must not peephole away side effectsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11Rename ConvertToSetZeroFlag to something more general.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10No need to recompute the SrcReg and CmpValue.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Move some of the decision logic for converting an instruction into one that setsBill Wendling
the 'zero' bit down into the back-end. There are other cases where this logic isn't sufficient, so they should be handled separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Modify the comparison optimizations in the peephole optimizer to update theBill Wendling
iterator when an optimization took place. This allows us to do more insane things with the code than just remove an instruction or two. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
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