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path: root/lib/CodeGen/MachineVerifier.cpp
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2012-07-25Verify two-address constraints more carefully.Jakob Stoklund Olesen
Include <undef> operands and virtual registers after leaving SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Fix crash in machine verifier when trying to print the def of a register ↵Pete Cooper
which has no def git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Check for extra kill flags on live-out virtual registers.Jakob Stoklund Olesen
This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen
Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Also verify the def index for early clobbers.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix some more LiveInterval enumerations.Jakob Stoklund Olesen
Deterministically enumerate the virtual registers instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158872 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka
the last instruction of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Move terminator machine verification to check ↵Pete Cooper
MachineBasicBlock::instr_iterator instead of MBB::iterator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen
Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen
No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Optional def can be either a def or a use (of reg0).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Fix a verifier bug.Jakob Stoklund Olesen
Make sure useless (def-only) intervals also get verified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen
The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen
The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Skip liveness verification when MRI->tracksLiveness() is false.Jakob Stoklund Olesen
Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Report the defining instruction.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Add SSA verification to MachineVerifier.Jakob Stoklund Olesen
Somehow we never verified SSA dominance before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Use SmallPtrSet instead of DenseSet.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper
static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Move the operand iterator into MachineInstrBundle.h where it belongs.Jakob Stoklund Olesen
Extract a base class and provide four specific sub-classes for iterating over const/non-const bundles/instructions. This eliminates the mystery bool constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Handle regmasks in the machine code verifier.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Update machine code verifier.Jakob Stoklund Olesen
After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Update MachineVerifier to check the new physreg live-in rules.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Remove all remaining uses of Value::getNameStr().Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Use getVNInfoBefore() when it makes sense.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen
The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Fix sub-register operand verification.Jakob Stoklund Olesen
PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Verify that terminators follow non-terminators.Jakob Stoklund Olesen
This exposes a -segmented-stacks bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick
This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15Stop verifying hasPHIKill() flags.Jakob Stoklund Olesen
There is only one legitimate use remaining, in addIntervalsForSpills(). All other calls to hasPHIKill() are only used to update PHIKill flags. The addIntervalsForSpills() function is part of the old spilling framework, only used by linearscan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-30Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen
The ARM target depends on CPSR liveness being tracked after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Don't check liveness of unallocatable registers.Jakob Stoklund Olesen
This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Check for multiple defs in the machine code verifier.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Revert r128961 because it didn't include a test and causes the verifier to failCameron Zwarich
on CodeGen/X86/2007-05-07-InvokeSRet.ll. There is probably a bug here that was fixed by r128961, but since there is no test or reference to a source file I have to revert it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04SjLj EH could produce a machine basic block that legitimately has more than oneBill Wendling
landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Permit blocks to branch directly to a landing pad.Jakob Stoklund Olesen
Treat the landing pad as a normal successor when that happens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128961 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Allow kill flags on two-address instructions. They are harmless.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Mark all uses as <undef> when joining a copy.Jakob Stoklund Olesen
This way, shrinkToUses() will ignore the instruction that is about to be deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like. Fix a misunderstanding in MachineVerifier about <def,undef> operands. The <undef> flag is valid on def operands where it has the same meaning as <undef> on a use operand. It only applies to sub-register defines which also read the full register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04Verify kill flags conservatively.Jakob Stoklund Olesen
Allow a live range to end with a kill flag, but don't allow a kill flag that doesn't end the live range. This makes the machine code verifier more useful during register allocation when kill flag computation is deferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-12Verify slot index ordering.Jakob Stoklund Olesen
The slot indexes must be monotonically increasing through the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-12Verify that machine instruction parent pointers are consistent.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08Fix a MachineVerifier loop that probably didn't mean to skip the last twoJakob Stoklund Olesen
virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-28Simplify some code in MachineVerifier that was doing the correct thing, but notCameron Zwarich
in the most obvious way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122610 91177308-0d34-0410-b5e6-96231b3b80d8
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