aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen/MachineScheduler.cpp
AgeCommit message (Collapse)Author
2012-05-24misched: rename ReadyQ classAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24misched: copy comments so compareRPDelta is readable by itself.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157424 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: trace ReadyQ.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157007 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: Added 3-level regpressure back-off.Andrew Trick
Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157005 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: fix liveness iteratorsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157003 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: tracing register pressure heuristics.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick
Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Release only unscheduled nodes into ReadyQ.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick
scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix a naughty header include that breaks "installed" builds.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: try (not too hard) to place debug values where they belongAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: ignore debug values during schedulingAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: DAG builder support for tracking register pressure within the ↵Andrew Trick
current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01misched: Add finalizeScheduler to complete the target interface.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: trace LiveIntervals after scheduling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: obvious iterator update fixes for bottom-up.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153160 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: cleanup main loopAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames
instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14Silence operator precedence warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14misched commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick
And add comments, since this is obviously confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched: handle scheduling region boundaries nicely.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick
not private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152374 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09revert 152356: verify misched changes using -misched=shuffle.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched: allow the default scheduler to be one chosen by the target.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08misched interface: Expose the MachineScheduler pass.Andrew Trick
Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
implement their own MachineScheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Added -view-misched=dags options.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched: Use the StartBlock/FinishBlock hooksAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Initialize SUnits before DAG building.Andrew Trick
Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Disentangle moving a machine instr from updating LiveIntervals.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08misched: bug in debug output.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08stale commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Add a "moveInstr" method to LiveIntervals. This can be used to move instructionsLang Hames
around within a basic block while maintaining live-intervals. Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API when reordering MIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick
ShuffleInstructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick
Responding to code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14misched: Initial code for building an MI level scheduling DAGAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-03 06:15:39 +0000