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path: root/lib/CodeGen/MachineRegisterInfo.cpp
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2010-10-06Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen
This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman
and to clean up unused incoming physregs from the live-in list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman
std::vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106298 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29Remove unused function.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29Remove schedule-livein-copies. It's not being used.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Avoid adding duplicate function live-in's.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13Add a utility function for conservatively clearing kill flags, and makeDan Gohman
use of it in MachineCSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Silence warningJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen
closure after allocating all blocks. Add a few more test cases for -regalloc=fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman
doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng
instructions for function arguments early and insert them after instruction selection is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26Insert dbg_value instructions for function entry block liveins (i.e. ↵Evan Cheng
function arguments). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Move the code for initialing the entry block livein set out ofDan Gohman
SelectionDAGISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Simplify a few more uses of reg_iterator.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng
MachineRegisterInfo. This allows more passes to set them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15Move MachineRegisterInfo::setRegClass out of line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08Move createVirtualRegister out-of-line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20Add a register class -> virtual registers map.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman
their cleanup code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53194 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13Added debugging routine dumpUses.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01switch the register iterator to act more like hte LLVM value iterator: ↵Chris Lattner
dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Add a trivial but handy function to efficiently return the machine Chris Lattner
instruction that defines the specified vreg. Crazy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Implement automatically updated def/use lists for all MachineInstr register Chris Lattner
operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
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