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path: root/lib/CodeGen/MachineLICM.cpp
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2012-02-08Codegen pass definition cleanup. No functionality.Andrew Trick
Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Move pass configuration out of pass constructors: MachineLICM.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Require non-NULL register masks.Jakob Stoklund Olesen
It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen
This fixes a typo in r148589. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Simplify debug output.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148723 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Support register masks in MachineLICM.Jakob Stoklund Olesen
Only PostRA LICM is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen
It is safe to move uses of such registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-1080 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Hoisted some loop invariant smallvector lookups out of a MachineLICM loopPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Changed MachineLICM to use a worklist list MachineCSE instead of recursion.Pete Cooper
Fixes <rdar://problem/10584116> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Disable LICM speculation in high register pressure situation again now that ↵Evan Cheng
Devang has fixed other issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20As Evan suggested, loads from constant pool are safe to speculate.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20Add a comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Constraint register class with constrainRegClass() to CSE a virtual into ↵Evan Cheng
another. rdar://10293289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17It is safe to speculate load from GOT. This fixes performance regression ↵Devang Patel
caused by r141689. Radar 10281206. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Tabs to spaces.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng
to investigate the regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Expand the check for a landing pad so that it looks at the basic block'sBill Wendling
containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix r141744.Evan Cheng
1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Refine r141689 with a tri-state variable.Evan Cheng
Also teach MachineLICM to avoid "speculation" when register pressure is high. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11N.B. This is with the new EH scheme:Bill Wendling
The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141569 and r141576.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. ↵Evan Cheng
Sorry, I can't come up with a small test case. rdar://10043690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng
MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng
more copies. rdar://9266679 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sorry, several patches in one.Evan Cheng
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Add a FIXME comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118803 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen
edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20More accurate estimate / tracking of register pressure.Evan Cheng
- Initial register pressure in the loop should be all the live defs into the loop. Not just those from loop preheader which is often empty. - When an instruction is hoisted, update register pressure from loop preheader to the original BB. - Treat only use of a virtual register as kill since the code is still SSA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116956 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20Make CodeGen TBAA-aware.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng
erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson
exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar
is", which breaks some nightly tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Fix for machine licm assert: RCCost <= RegPressure[RCId]Andrew Trick
in MultiSource/Benchmarks/VersaBench/beamformer/beamformer. SmallSet.insert returns true if the element is inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19- Add a hook for target to determine whether an instruction def isEvan Cheng
"long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16More machine LICM work. It now tracks register pressure for path from ↵Evan Cheng
preheader to current BB and use the information determine whether hoisting is worthwhile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14Register pressure and instruction latency aware machine LICM. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12Begin adding static dependence information to passes, which will allow us toOwen Anderson
perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8
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