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basic block, not at the first
instruction. Also, their valno's should have an unknown def. This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
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isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
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remat and splitting.
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appropriate.
With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.
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1) Assign stack slots to new temporaries.
2) Don't insert an interval into the return vector more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54956 91177308-0d34-0410-b5e6-96231b3b80d8
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1) Remove an incorrect assertion.
2) Set the stack slot weight properly.
3) Resize the VirtRegMap when needed.
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sorted by starting index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54939 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineRegisterInfo::reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54930 91177308-0d34-0410-b5e6-96231b3b80d8
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remat, or splitting. This code has been updated to current APIs
in so far as it compiles and, in theory, works, but does not take advantage of recent advancements. For instance, it could be improved by using
MachineRegisterInfo::use_iterator.
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the r2iMap_ by value. This will prevent references to them from being invalidated
if the map is changed.
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remapped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54218 91177308-0d34-0410-b5e6-96231b3b80d8
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a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.
Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.
Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.
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to fix this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54072 91177308-0d34-0410-b5e6-96231b3b80d8
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a PHI has been removed. The interval previously defined
by the PHI needs to be extended to the beginning of its basic block, and the intervals that were inputs need to be trimmed to the end
of their basic blocks.
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robust.
This is tricky business, and will probably take a few more iterations to get
the last kinks out of it.
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regressions, such as PR2595. Also, there is a significant code-quality
issue in SPEC 464.h264ref and a few others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54014 91177308-0d34-0410-b5e6-96231b3b80d8
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AliasAnalysis::pointsToConstantMemory,
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54000 91177308-0d34-0410-b5e6-96231b3b80d8
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renumbering possible.
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forgot
to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.
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live intervals itself to use an instruction count approximation that is
not affected by inserting empty indices.
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Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.
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register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8 %reg1024<def> = IMPLICIT_DEF
12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53503 91177308-0d34-0410-b5e6-96231b3b80d8
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the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53394 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
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propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
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the list to find it again later.
This speeds up live intervals from 0.37s to 0.30s on instcombine.
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we can more easily
add new instructions.
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impact on code quality or compile time.
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StrongPHIElimination in the near future.
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to the end of its MBB.
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