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path: root/lib/CodeGen/LLVMTargetMachine.cpp
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2010-11-19Change some methods in MCDwarf.cpp to be able to handle an arbitraryRafael Espindola
MCStreamer instead of just MCObjectStreamer. Address changes cannot be as efficient as we have to use DW_LNE_set_addres, but at least most of the logic is shared. This will be used so that, with CodeGen still using EmitDwarfLocDirective, llvm-gcc is able to produce debug_line sections without needing an assembler that supports .loc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119777 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Oops, missed this file when remaing ExpandPseudos to ExpandISelPseudos.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Split pseudo-instruction expansion into a separate pass, to make itDan Gohman
easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add registry hook for assembly text outputChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18Add TypeBasedAliasAnalysis to the standard pass lists. Note that itDan Gohman
is currently inert by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18Make BasicAliasAnalysis a normal AliasAnalysis implementation whichDan Gohman
does normal initialization and normal chaining. Change the default AliasAnalysis implementation to NoAlias. Update StandardCompileOpts.h and friends to explicitly request BasicAliasAnalysis. Update tests to explicitly request -basicaa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08Call InitSections in llc and clang so that the binaries produced by themRafael Espindola
are easier to diff with those produced by llvm-mc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Stop using the dom frontier in DwarfEHPrepare by not promoting alloca'sDuncan Sands
any more. I plan to reimplement alloca promotion using SSAUpdater later. It looks like Bill's URoR logic really always needs domtree, so the pass now always asks for domtree info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Move enabling the local stack allocation pass into the target where it belongs.Jim Grosbach
For now it's still a command line option, but the interface to the generic code doesn't need to know that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14Add a local stack object block allocation pass. This is still anJim Grosbach
experimental pass that allocates locals relative to one another before register allocation and then assigns them to actual stack slots as a block later in PEI. This will eventually allow targets with limited index offset range to allocate additional base registers (not just FP and SP) to more efficiently reference locals, as well as handle situations where locals cannot be referenced via SP or FP at all (dynamic stack realignment together with variable sized objects, for example). It's currently incomplete and almost certainly buggy. Work in progress. Disabled by default and gated via the -enable-local-stack-alloc command line option. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13tidy up whitespace a bitJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizerBill Wendling
pass. This pass should expand with all of the small, fine-grained optimization passes to reduce compile time and increase happiment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Add the Optimize Compares pass (disabled by default).Bill Wendling
This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Remove double-def checking from MachineVerifier, so a register does not have toJakob Stoklund Olesen
be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04The lower invoke pass needs to have unreachable code elimination run after itBill Wendling
because it could create such things. This fixes a MingW buildbot test failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04The EH prepare passes really want to be the last passes run before code-gen.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ↵Benjamin Kramer
ownership of the TargetAsmBackend and the MCCodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Initial modifications to MCAssembler and TargetMachine for the MCJIT.Reid Kleckner
Patch by Olivier Meurant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman
- Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09--- Reverse-merging r107947 into '.':Bob Wilson
U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman
Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman
a separate DCE pass over MachineInstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01Temporarily disable on-demand fast-isel.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01Fast isel no longer needs DeadMachineInstrElim to clean up after it.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Add some comments.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen
optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26MC: Add TargetMachine support for setting the value of MCRelaxAll withDaniel Dunbar
-filetype=obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18llc (et al): Add support for --show-encoding and --show-inst.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14XFAIL the test I added with vg_leak, apparently it is the first and only llcDaniel Dunbar
-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we need to sort out the ownership model for the various MC objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19Code that needs a TargetMachine should have access to one directly, ratherDan Gohman
than just getting one through a TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Fix codegen passes. -disable-ssc shouldn't disable postra machine licm.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12Enable post regalloc machine licm by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov
It is not ready for public yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Post regalloc LICM. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100592 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04Momentous day: remove the "O" member from AsmPrinter. Now all Chris Lattner
"asm printering" happens through MCStreamer. This also Streamerizes PIC16 debug info, which escaped my attention. This removes a leak from LLVMTargetMachine of the 'legacy' output stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04fix an ugly wart in the MCInstPrinter api where theChris Lattner
raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13rearrange MCContext ownership. Before LLVMTargetMachine created it Chris Lattner
and passing off ownership to AsmPrinter. Now MachineModuleInfo creates it and owns it by value. This allows us to use MCSymbols more consistently throughout the rest of the code generator, and simplifies a bit of code. This also allows MachineFunction to keep an MCContext reference handy, and cleans up the TargetRegistry interfaces for AsmPrinters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-12make the mangler take an MCContext instead of an MAI.Chris Lattner
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-12remove MAI argument from createAsmStreamer since itChris Lattner
can get it from the context now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11change MCContext to always have an MCAsmInfo.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11MC: Provide MCAssembler with a TargetAsmBackend.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10Enable machine cse pass.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09Revert accidental commit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09- Make the machine cse dumb coalescer (as opposed to the more awesome simpleEvan Cheng
coalescer) handle sub-register classes. - Add heuristics to avoid non-profitable cse. Given the current lack of live range splitting, avoid cse when an expression has PHI use and the would be new use is in a BB where the expression wasn't already being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05We don't really care about correct register liveness information after theJakob Stoklund Olesen
post-ra scheduler has run. Disable the verifier checks that late in the game. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97837 91177308-0d34-0410-b5e6-96231b3b80d8
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