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Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
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the rich disassembly of a complete object or executable.
These are very much a work in progress, and not really useful yet.
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No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
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return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
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#line directives with the needed support in the lexer. Next will be to build
a simple file/line# table mapping source SMLoc's for later use by diagnostics.
And the last step will be to get the diagnostics to use the mapping for file
and line numbers.
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handling to llvm-mc. Reviewed by Owen Anderson.
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- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
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In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.
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Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
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from MC.
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instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.
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The argument is unused, and is a layering violation in any case.
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Thanks to Jonas Gafele for noticing.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
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No need for it to be redefined as part of every derived target asm parser
class.
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of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
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externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.
Fixes PR10420.
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the disassembler, where we may realize fairly late into decoding that something is wrong and need to reset.
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MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
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createMCAsmBackend.
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should be faster and smaller.
Goodbye static ctors and dtors!
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they belong.
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- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.
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There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.
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- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
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TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
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(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
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better location welcome).
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to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
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solution but it is a small step towards removing the horror that is
TargetAsmInfo.
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