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ridiculously ginormous patterns and need more than one byte
of displacement for encodings. This fixes CellSPU/fdiv.ll.
SPU is still doing something else ridiculous though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96833 91177308-0d34-0410-b5e6-96231b3b80d8
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isel doesn't know the correct # results. This fixes 8 codegen tests,
down to 22 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96815 91177308-0d34-0410-b5e6-96231b3b80d8
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has one of the list of acceptable opcodes for a complex
pattern. This fixes 4 regtest failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96814 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96779 91177308-0d34-0410-b5e6-96231b3b80d8
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CodeGen/X86/pr2182.ll. Down to 13 x86 failures out of ~1100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96770 91177308-0d34-0410-b5e6-96231b3b80d8
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result nodes correctly. Note that this includes a horrible hack
in DAGISelHeader which cannot be fixed reasonably without
eliminating (parallel) from input patterns. That, in turn,
can't be done until we support writing multiple result patterns
for the X86and_flag and related multiple-result nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96767 91177308-0d34-0410-b5e6-96231b3b80d8
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for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.
This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96755 91177308-0d34-0410-b5e6-96231b3b80d8
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MVT::iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96753 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96752 91177308-0d34-0410-b5e6-96231b3b80d8
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utility. Down to 6 ppc failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96751 91177308-0d34-0410-b5e6-96231b3b80d8
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<4 x i32> with <4 x float> values if they end up the same
register class. This gets us up to 231 passes on the ppc
tests (only 7 fails).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96750 91177308-0d34-0410-b5e6-96231b3b80d8
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sync with the top of stack. This fixes a bunch of failures on larger
testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96732 91177308-0d34-0410-b5e6-96231b3b80d8
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of the matched pattern to use the newly created node results. Onto
the "making it actually work" phase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96724 91177308-0d34-0410-b5e6-96231b3b80d8
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the point where it is to the 95% feature complete mark, it just
needs result updating to be done (then testing, optimization
etc).
More specificallly, this adds support for chain and flag handling
on the result nodes, support for sdnodexforms, support for variadic
nodes, memrefs, pinned physreg inputs, and probably lots of other
stuff.
In the old DAGISelEmitter, this deletes the dead code related to
OperatorMap, cleans up a variety of dead stuff handling "implicit
remapping" from things like globaladdr -> targetglobaladdr (which
is no longer used because globaladdr always needs to be legalized),
and some minor formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96716 91177308-0d34-0410-b5e6-96231b3b80d8
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ARM and Thumb tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96663 91177308-0d34-0410-b5e6-96231b3b80d8
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This hopefulyl should unbreak EH on PPC/Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96637 91177308-0d34-0410-b5e6-96231b3b80d8
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index
which is not always true if the mask contains undefs. Modified it to return
the first non undef value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96621 91177308-0d34-0410-b5e6-96231b3b80d8
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building the tree to represent them but not emitting
table entries for them yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96617 91177308-0d34-0410-b5e6-96231b3b80d8
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Moderate the weight given to very small intervals.
The spill weight given to new intervals created when spilling was not
normalized in the same way as the original spill weights calculated by
CalcSpillWeights. That meant that restored registers would tend to hang around
because they had a much higher spill weight that unspilled registers.
This improves the runtime of a few tests by up to 10%, and there are no
significant regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96613 91177308-0d34-0410-b5e6-96231b3b80d8
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CSE'd or otherwise combined with temporal MemSDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96505 91177308-0d34-0410-b5e6-96231b3b80d8
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and add a sparc implementation that knows about delay slots. Patch by
Nathan Keynes!
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I'd like to eventually rip it out, but for now producing the
same selections as the old matcher is more important.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96458 91177308-0d34-0410-b5e6-96231b3b80d8
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functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96453 91177308-0d34-0410-b5e6-96231b3b80d8
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CheckComplexPattern function. Though it is logically const,
I don't have the fortitude to clean up all the targets now,
and it not being const doesn't block anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96426 91177308-0d34-0410-b5e6-96231b3b80d8
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use and only call IsProfitableToFold/IsLegalToFold on the load
being folded, like the old dagiselemitter does. This
substantially simplifies the code and improves opportunities for
sharing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96368 91177308-0d34-0410-b5e6-96231b3b80d8
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build if enabled, it will fail with constness issues. I'll resolve
these next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96336 91177308-0d34-0410-b5e6-96231b3b80d8
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(isprofitable|islegal)tofold checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96331 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
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Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96285 91177308-0d34-0410-b5e6-96231b3b80d8
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IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
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produce a table based matcher instead of gobs of C++ Code.
Though it's not done yet, the shrinkage seems promising,
the table for the X86 ISel is 75K and still has a lot of
optimization to come (compare to the ~1.5M of .o generated
the old way, much of which will go away).
The code is currently disabled by default (the #if 0 in
DAGISelEmitter.cpp). When enabled it generates a dead
SelectCode2 function in the DAGISel Header which will
eventually replace SelectCode.
There is still a lot of stuff left to do, which are
documented with a trail of FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96215 91177308-0d34-0410-b5e6-96231b3b80d8
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many other natural things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96214 91177308-0d34-0410-b5e6-96231b3b80d8
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packing somewhat densely is better than not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96213 91177308-0d34-0410-b5e6-96231b3b80d8
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created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96069 91177308-0d34-0410-b5e6-96231b3b80d8
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This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95980 91177308-0d34-0410-b5e6-96231b3b80d8
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reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
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different word was intended.
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