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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12569 91177308-0d34-0410-b5e6-96231b3b80d8
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it is always completely initialized and copied.
Also, fix up many comments and asserts.
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annotable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11978 91177308-0d34-0410-b5e6-96231b3b80d8
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methods take an int or unsigned value instead of int64_t.
Also, add an 'addImm' method to the MachineInstrBuilder class, because the
fact that the hardware sign or zero extends it does not/should not matter
to the code generator. Once the old sparc backend is removed the difference
can be eliminated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11975 91177308-0d34-0410-b5e6-96231b3b80d8
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each MachineOperand. We don't really need an int64_t immediate :-).
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to objects.
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block into MachineBasicBlock::getFirstTerminator().
This also fixes a bug in the implementation of the above in both
RegAllocLocal and InstrSched, where instructions where added after the
terminator if the basic block's only instruction was a terminator (it
shouldn't matter for RegAllocLocal since this case never occurs in
practice).
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parts of the compiler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11719 91177308-0d34-0410-b5e6-96231b3b80d8
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switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11715 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11711 91177308-0d34-0410-b5e6-96231b3b80d8
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leave register operands with the same use/def flags as the original
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11709 91177308-0d34-0410-b5e6-96231b3b80d8
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Also make it less aggressive as the current implementation breaks in
some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11696 91177308-0d34-0410-b5e6-96231b3b80d8
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1. LiveIntervals now implement a 4 slot per instruction model. Load,
Use, Def and a Store slot. This is required in order to correctly
represent caller saved register clobbering on function calls,
register reuse in the same instruction (def resues last use) and
also spill code added later by the allocator. The previous
representation (2 slots per instruction) was insufficient and as a
result was causing subtle bugs.
2. Fixes in spill code generation. This was the major cause of
failures in the test suite.
3. Linear scan now has core support for folding memory operands. This
is untested and not enabled (the live interval update function does
not attempt to fold loads/stores in instructions).
4. Lots of improvements in the debugging output of both live intervals
and linear scan. Give it a try... it is beautiful :-)
In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.
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given a register.
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Move out of line member functions of MachineBasicBlock to
MachineBasicBlock.cpp.
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Whitespace cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11388 91177308-0d34-0410-b5e6-96231b3b80d8
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Add prototypes for MachineBasicBlock's dump() and print() methods.
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MachineBasicBlock. Also change opcode to a short and numImplicitRefs
to an unsigned char so that overall MachineInstr's size stays the
same.
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means of default arguments.
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ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
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methods which have strangely different semantics in different backends,
and noone knew what any did.
Getting rid of these ALSO allows the dependence of MachineInstr.h on
MRegisterInfo.h to be removed, which makes me much happier, and probably
alkis too. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11287 91177308-0d34-0410-b5e6-96231b3b80d8
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MRegisterInfo::isPhysicalRegister(MO.getReg()) and the Sparc backend should
use isMachineRegister()
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operand of the instruction and thus simplify the register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11124 91177308-0d34-0410-b5e6-96231b3b80d8
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Take away the default iostream argument of createMachineFunctionPrinterPass(),
at Chris's request.
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spilled, A was loaded from its stack location twice. This fixes the bug.
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TwoAddressInstructionPass can correctly update use/def information.
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