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2013-05-21The RecordMetadataForSrpc function that was removed initialized ↵Eli Bendersky
NaClRecordObjectInformation, and this initialization has to be reinstated. BUG=None R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15451003
2013-05-21Merging r182344:Bill Wendling
------------------------------------------------------------------------ r182344 | mren | 2013-05-20 17:57:22 -0700 (Mon, 20 May 2013) | 7 lines Dwarf: use a single line table to generate assembly when .loc is used. This is to fix PR15408 where an undefined symbol Lline_table_start1 is used. Since we do not generate the debug_line section when .loc is used, Lline_table_start1 is not emitted and we can't refer to it when calculating at_stmt_list for a compile unit. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20Create type IDs based on reference counts.Karl Schimpf
Create type IDs based on number of references, rather than first reached. This is done so that fewer bits are used to encode types that are commonly used. Note that this cuts the size of the generate bitcode file by about 1.5%, with no effect on the reader, since it only changes the order type ID's are created. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3405 R=jvoung@chromium.org Review URL: https://codereview.chromium.org/14495008
2013-05-20Fix stderr redirection in test to work on all platformsEli Bendersky
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/15470008
2013-05-20Remove 'svn' from version.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20Remove the 'svn' from the version.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182311 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20PNaCl: Fix FlattenGlobals to correctly handle implicitly-aligned variablesMark Seaborn
If a global variable has no "align" attribute, it must be aligned based on its type. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3437 TEST=flatten-globals.ll Review URL: https://codereview.chromium.org/15359006
2013-05-17Merging r182113:Bill Wendling
------------------------------------------------------------------------ r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines R600: Fix encoding for R600 family GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.Jan Voung
There was an old fix for r+r based memory references on x86-64 that checked for isTargetNaCl() instead of isTargetNaCl64(). This disabled some r+r for 32-bit. However, fast isel only sets up r+r with geps, and we don't have geps in the stable ABI. We could potentially add some similar pattern matching in the future... The problem we *do* see with the current bitcode, is that this change also made it preferred to use an index register instead of a base register. This made the memory references on x86-32 look like: cmpl ..., (,%eax,1) instead of cmpl ..., (%eax) So we had longer instructions. Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%) Total not zipped: 17.28MB vs 16.28 MB (6%) runtime diffs (min of 5 runs) * eon 4.94 (old) vs 4.72 (new) (~4%) * mesa 21.64 vs 21.08 * mcf 5.76 vs 5.60 * vortex 4.21 vs 4.05 * perlbmk 27.62 vs 26.55 (the rest were under 2% better) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/15047013
2013-05-17Merging r181864:Bill Wendling
------------------------------------------------------------------------ r181864 | chapuni | 2013-05-14 19:16:23 -0700 (Tue, 14 May 2013) | 10 lines ELFRelocationEntry::operator<(): Try to stabilize the order. r_offset was insufficient to sort Relocs. It should fix llvm/test/CodeGen/ARM/ehabi-mc-compact-pr*.ll on some hosts. RELOCATION RECORDS FOR [.ARM.exidx]: 0 R_ARM_PREL31 .text 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 FIXME: I am not sure of the directions of extra comparators, in Type and Index. For now, they are different from the direction in r_offset. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r181706:Bill Wendling
------------------------------------------------------------------------ r181706 | rafael | 2013-05-13 07:34:48 -0700 (Mon, 13 May 2013) | 1 line Remove unused fields and arguments. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r181678:Bill Wendling
------------------------------------------------------------------------ r181678 | rafael | 2013-05-12 17:18:24 -0700 (Sun, 12 May 2013) | 1 line XFAIL this test for mingw too. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r181600:Bill Wendling
------------------------------------------------------------------------ r181600 | aaronballman | 2013-05-10 07:42:16 -0700 (Fri, 10 May 2013) | 1 line XFAILing this test on Win32 to unbreak the build bots. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r182072:Bill Wendling
------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Cherry-pick r181922: Fix miscompile due to StackColoring incorrectly merging ↵Mark Seaborn
stack slots (PR15707) IR optimisation passes can result in a basic block that contains: llvm.lifetime.start(%buf) ... llvm.lifetime.end(%buf) ... llvm.lifetime.start(%buf) Before this change, calculateLiveIntervals() was ignoring the second lifetime.start() and was regarding %buf as being dead from the lifetime.end() through to the end of the basic block. This can cause StackColoring to incorrectly merge %buf with another stack slot. Fix by removing the incorrect Starts[pos].isValid() and Finishes[pos].isValid() checks. Just doing: Starts[pos] = Indexes->getMBBStartIdx(MBB); Finishes[pos] = Indexes->getMBBEndIdx(MBB); unconditionally would be enough to fix the bug, but it causes some test failures due to stack slots not being merged when they were before. So, in order to keep the existing tests passing, treat LiveIn and LiveOut separately rather than approximating the live ranges by merging LiveIn and LiveOut. This fixes PR15707. Patch by Mark Seaborn. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3374 Review URL: https://codereview.chromium.org/15302009
2013-05-16Temporarily remove test that fails on MacEli Bendersky
BUG=None Review URL: https://codereview.chromium.org/15100013
2013-05-16Merging r181529:Bill Wendling
------------------------------------------------------------------------ r181529 | void | 2013-05-09 11:21:45 -0700 (Thu, 09 May 2013) | 8 lines Simplify the code a bit. The compact unwind registers were defined in two different places. It's better just to place them in the function that uses them and specify that this is a 64-bit or 32-bit machine. No functionality change. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181540:Bill Wendling
------------------------------------------------------------------------ r181540 | void | 2013-05-09 13:10:38 -0700 (Thu, 09 May 2013) | 11 lines Generate a compact unwind encoding in the face of a stack alignment push. We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181580:Bill Wendling
------------------------------------------------------------------------ r181580 | tstellar | 2013-05-09 19:09:45 -0700 (Thu, 09 May 2013) | 10 lines R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181579:Bill Wendling
------------------------------------------------------------------------ r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines R600: Expand SUB for v2i32/v4i32 Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181578:Bill Wendling
------------------------------------------------------------------------ r181578 | tstellar | 2013-05-09 19:09:34 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand MUL for v4i32/v2i32 Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181577:Bill Wendling
------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181576:Bill Wendling
------------------------------------------------------------------------ r181576 | tstellar | 2013-05-09 19:09:24 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand vselect for v4i32 and v2i32 v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181792:Bill Wendling
------------------------------------------------------------------------ r181792 | tstellar | 2013-05-14 07:42:56 -0700 (Tue, 14 May 2013) | 8 lines R600/SI: Add processor type for Hainan asic Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Merging r181842:Bill Wendling
------------------------------------------------------------------------ r181842 | arnolds | 2013-05-14 15:33:24 -0700 (Tue, 14 May 2013) | 14 lines ARM ISel: Don't create illegal types during LowerMUL The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Merging r181524:Bill Wendling
------------------------------------------------------------------------ r181524 | rafael | 2013-05-09 10:22:59 -0700 (Thu, 09 May 2013) | 4 lines Don't replace an alias in llvm.used with its target. When we replace an internal alias with its target, be careful not to replace the entry in llvm.used (and llvm.compiler_used). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181909 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Separate the PNaCl llc into a tool named pnacl-llc (how original!)Eli Bendersky
BUG=None R=jvoung@chromium.org Review URL: https://codereview.chromium.org/14604011
2013-05-14Update tests to use FileCheck instead of grep (which is deprecated in the ↵Eli Bendersky
LLVM regression suite) BUG=None R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/15042009
2013-05-14The customary LLVM way of obtaining intrinsics is withEli Bendersky
Intrinsic::getDeclaration and use the definition in include/llvm/Intrinsics.td This also makes the attribute on the intrinsic to be more consistent with the back-end (code-gen), which automatically assumes it's ReadNone (because this is what Intrinsics.td) defines. Using ReadNone rather than ReadOnly may be not strictly correct because the intrinsic depends on the value of the TP. However, this attribute is not really used anywhere in IR optimizations, and in the backend the intrinsic is ReadNone anyhow (the IR setting gets overridden). If we run into any problems with this in the future, we may consider handling the lowering of this intrinsic in TargetLowering::LowerINTRINSIC_W_CHAIN rather than in TargetLowering::LowerINTRINSIC_WO_CHAIN. BUG=None R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14643019
2013-05-14Fix some build warnings in Nacl-specific codeEli Bendersky
BUG=None R=dschuff@chromium.org Review URL: https://codereview.chromium.org/14840018
2013-05-14Merging r181450:Bill Wendling
------------------------------------------------------------------------ r181450 | uweigand | 2013-05-08 10:50:07 -0700 (Wed, 08 May 2013) | 16 lines [PowerPC] Fix regression in generating @ha/@l relocs The patch I committed as revision 167864 introduced a regression that causes LLVM to no longer generate appropriate relocs for @ha/@l symbol references (but fail an assertion instead). This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/ VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in PPCELFObjectWriter.cpp. Tested by running projects/test-suite in -m32 mode with the integrated assembler forced on. A standalone test case will be committed shortly as well. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Merging r181800:Bill Wendling
------------------------------------------------------------------------ r181800 | wschmidt | 2013-05-14 09:08:32 -0700 (Tue, 14 May 2013) | 15 lines PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Merging r181586:Bill Wendling
------------------------------------------------------------------------ r181586 | d0k | 2013-05-10 02:16:52 -0700 (Fri, 10 May 2013) | 3 lines InstCombine: Verify the type before transforming uitofp into select. PR15952. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Adding a pass - RewritePNaClLibraryCalls, that replaces known library calls ↵Eli Bendersky
with stable bitcode intrinsics. Starting with setjmp and longjmp. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=jvoung@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/14617017
2013-05-14Update PNaCl intrinsic whitelist test for moving {frame,return}address to ↵Jan Voung
blacklist. Forgot to do this in last CL: https://codereview.chromium.org/14657017/ BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/14774009
2013-05-13Start to disallow llvm.frameaddress and llvm.returnaddress in ABI checker.Jan Voung
They do not seem to be widely used by user code. * The boehm garbage collector library does reference __builtin_return_address under an ifdef, but it does not appear to be compiled in. * Mesa-7.6 uses __builtin_frame_address for u_debug_stack.c, but that also does not appear to be part of the built libraries. They expose stack/code addresses (at least the lower 32-bits of the address). As part of https://codereview.chromium.org/14619022/, we stopped considering the scons and gcc torture tests that use these intrinsics as meeting the stable ABI. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/14657017
2013-05-10PNaCl ABI: Promote illegal integer typesDerek Schuff
This pass (mostly) legalizes integer types by promoting them. It has some limitations (e.g. it can't change function types) but it is more than sufficient for what clang and SROA generate. A more significant limitation of promotion is that packed bitfields of size > 64 bits are still not handled. There are none in our tests (other than callingconv_case_by_case which doesn't require a stable pexe) but we will want to either handle them by correctly expanding them, or find a better way to error out. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3360 R=eliben@chromium.org, jvoung@chromium.org Review URL: https://codereview.chromium.org/14569012
2013-05-10LLVM: Add ELF Note section to NaCl object files identifying them as such to goldDerek Schuff
This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009
2013-05-10Fixing MCJIT unit test on Windows.Andrew Kaylor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10Merging r181397:Bill Wendling
------------------------------------------------------------------------ r181397 | nicholas | 2013-05-08 02:00:10 -0700 (Wed, 08 May 2013) | 3 lines Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInst by switching to a ValueMap. Patch by Andrea DiBiagio! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09Support @llvm.nacl.{set|long}jmp intrinsics by translating them to library callsEli Bendersky
This is similar to the way @llvm.{set|long}jmp are handled. The previously defined nacl-specific intrinsics are no longer used and are overridden. For the library call, call setjmp/longjmp without a preceding underscore as these symbols exist in our runtime support code (pnacl/support/setjmp_XXX.S) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14715018
2013-05-09Move llvm.eh.frame.cfa to the blacklist of intrinsics.Jan Voung
Tests that use them now skip ABI verification. Known tests that use this are the scons tests: - the barebones_stack_alignment16 test and - the EH ones under tests/toolchain/ Also list other eh_* in the blacklist more explicitly (they were already caught by the default case). BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378 TEST= scons, gcc torture, llvm R=dschuff@chromium.org Review URL: https://codereview.chromium.org/14998008
2013-05-09Add a llvm lit test for NaCl ARM/X86 support for bswap i16, i32, i64.Jan Voung
Slowly trying to promote "dev" intrinsics that are being tested to be accepted. Luckily, bswap is supported without compiler_rt for ARM and x86 at least. Test at default level and -O0. Also tested by gcc/testsuite/gcc.dg/builtin-bswap-[1,2,3,4,5].c, and a couple of other gcc tests. We may want to blacklist odd argument sizes like i8, and i1, which the x86 backend won't handle. The i16 case is also interesting, however, it's easy to do if you have an i32 bswap. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3378 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14971004
2013-05-09PNaCl: Add NoAlias attributes in ExpandByVal and ExpandVarArgs passesMark Seaborn
This could help prevent these expansion passes from inhibiting optimisations than run after the expansion. e.g. It gives the optimiser more freedom to move around reads from the varargs buffer because they will not alias writes to other locations. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3400 TEST=PNaCl toolchain trybots + GCC torture tests + LLVM test suite + Spec2k Review URL: https://codereview.chromium.org/14060026
2013-05-09Merging r181423:Bill Wendling
------------------------------------------------------------------------ r181423 | hfinkel | 2013-05-08 05:16:14 -0700 (Wed, 08 May 2013) | 5 lines PPCInstrInfo::optimizeCompareInstr should not optimize FP compares The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Add dependency on NaClTransforms to lib/Target/ARM.Jan Voung
It depends on NaClTransforms for the denominator zero checks transform. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2833 (fix build) R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15067004
2013-05-08Merging r181286:Bill Wendling
------------------------------------------------------------------------ r181286 | arnolds | 2013-05-06 21:37:05 -0700 (Mon, 06 May 2013) | 7 lines LoopVectorize: getConsecutiveVector must respect signed arithmetic We were passing an i32 to ConstantInt::get where an i64 was needed and we must also pass the sign if we pass negatives numbers. The start index passed to getConsecutiveVector must also be signed. Should fix PR15882. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Put llvm.powi in the dev list of intrinsics.Jan Voung
This is used by the LLVM translator as part of: lib/Analysis/ConstantFolding.cpp (it tries to do constant folding for pow calls...) Also, tweak comment about llvm.pow vs llvm.powi. It looks like powi is the imprecise one, not pow. BUG=unblock DEPs roll, broken self-build. BUG=http://code.google.com/p/nativeclient/issues/detail?id=3378 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14631013
2013-05-08Insert denominator zero checks for NaClDavid Sehr
This IR pass for ARM inserts a comparison and a branch to trap if the denominator of a DIV or REM instruction is zero. This makes ARM fault identically to x86 in this case. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2833 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14607004
2013-05-08Merge of r181434Richard Sandiford
Add myself as SystemZ code owner git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181435 91177308-0d34-0410-b5e6-96231b3b80d8
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