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with other code related to shuffles and easier to implement in compiled code.
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'SIZE' and 'LENGTH' operators.
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They were added a while back to debug the use of self-deleting temp files.
Remove now, otherwise buildbot logs will show this spew.
BUG=none
Review URL: https://codereview.chromium.org/11981003
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self-hosted LTO build bots.
Okay, here's how to reproduce the problem:
1) Build a Release (or Release+Asserts) version of clang in the normal way.
2) Using the clang & clang++ binaries from (1), build a Release (or
Release+Asserts) version of the same sources, but this time enable LTO ---
specify the `-flto' flag on the command line.
3) Run the ARC migrator tests:
$ arcmt-test --args -triple x86_64-apple-darwin10 -fsyntax-only -x objective-c++ ./src/tools/clang/test/ARCMT/cxx-rewrite.mm
You'll see that the output isn't correct (the whitespace is off).
The mis-compile is in the function `RewriteBuffer::RemoveText' in the
clang/lib/Rewrite/Core/Rewriter.cpp file. When that function and RewriteRope.cpp
are compiled with LTO and the `arcmt-test' executable is regenerated, you'll see
the error. When those files are not LTO'ed, then the output of the `arcmt-test'
is fine.
It is *really* hard to get a testcase out of this. I'll file a PR with what I
have currently.
--- Reverse-merging r172363 into '.':
U include/llvm/Analysis/MemoryBuiltins.h
U lib/Analysis/MemoryBuiltins.cpp
--- Reverse-merging r171325 into '.':
U test/Transforms/InstCombine/objsize.ll
G include/llvm/Analysis/MemoryBuiltins.h
G lib/Analysis/MemoryBuiltins.cpp
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This is the skeleton for a verifier for the portion of the PNaCl bitcode ABI
that can be verified after the bitcode has been read into a Module object.
There is a ModulePass for module-level rules (e.g. GV linkage types) and a
FunctionPass for rules that apply to function bodies (e.g. legal instructions).
They are separated this way to keep the verifier streaming-friendly.
For now, the passes are registered but not hooked up, so they can only be run
manually via opt.
There are 2 bits of actual functionality, just so each pass has something to do:
The ModulePass checks the linkage types of GVs, and the FunctionPass checks
instruction opcodes. For now only the terminator instructions are checked, but
the idea is to add the rest of the allowed instructions to the whitelist,
and possibly call operand checks from the switch statement as well.
For now we just print messagees to stderr, but we will probably want a better
way to plumb the errors in the browser in the future.
R=jvoung@chromium.org,sehr@chromium.org
BUG= https://code.google.com/p/nativeclient/issues/detail?id=2196
Review URL: https://codereview.chromium.org/11986002
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instruction as it doesn't exist on all x64 CPU architectures.
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- This code is dead, and the "right" way to get this support is to use the
platform-specific linker-integrated LTO mechanisms, or the forthcoming LLVM
linker.
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calling convention. 128-bit integers are now properly returned
in GPR3 and GPR4 on PowerPC.
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Part of rdar://12576868
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branch).
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This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902
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``Visited'' Debug message to use it.
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doesn't exist on all CPU architectures. Fixes PR14982
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_Complex float and _Complex long double, by simply increasing the
number of floating point registers available for return values.
The test case verifies that the correct registers are loaded.
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the values of shadow scale and offset to the runtime
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v8i8 -> v8i64,
v8i8 -> v8i32,
v4i8 -> v4i64,
v4i16 -> v4i64
for AVX and AVX2.
Bug 14865.
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they get instantiated together.
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changing both the string of the dwo_name to be correct and the type of
the statement list.
Testcases all around.
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emitting the dwarf32 version of DW_FORM_sec_offset and correct
disassembler support.
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Let targets use it.
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Move the early if-conversion pass into this group.
ILP optimizations usually need to find the right balance between
register pressure and ILP using the MachineTraceMetrics analysis to
identify critical paths and estimate other costs. Such passes should run
together so they can share dominator tree and loop info analyses.
Besides if-conversion, future passes to run here here could include
expression height reduction and ARM's MLxExpansion pass.
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but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
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ambiguous term 'legal'.
Suggested by Andrew Booker. Thanks Andrew!
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Reported on IRC by _savage
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Moving the X86CostTable to a common place, so that other back-ends
can share the code. Also simplifying it a bit and commoning up
tables with one and two types on operations.
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Patch by Jakub Staszak.
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return into the safe harbor of AsmParser's private areas.
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