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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175626 91177308-0d34-0410-b5e6-96231b3b80d8
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sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
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It is possible that frame pointer is not found in the
callee saved info, thus FramePtrSpillFI may be incorrect
if we don't check the result of hasFP(MF).
Besides, if we enable the stack coloring algorithm, there
will be an assertion to ensure the slot is live. But in
the test case, %var1 is not live in the prologue of the
function, and we will get the assertion failure.
Note: There is similar code in ARMFrameLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175616 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175609 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175608 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175607 91177308-0d34-0410-b5e6-96231b3b80d8
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function attributes.
This makes the LLVM assembly look better. E.g.:
define void @foo() #0 { ret void }
attributes #0 = { nounwind noinline ssp }
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175605 91177308-0d34-0410-b5e6-96231b3b80d8
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common transformations. This includes updating repairIntervalsInRange() to
handle more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175604 91177308-0d34-0410-b5e6-96231b3b80d8
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correct value is needed in every iteration of the loop for updating
LiveIntervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175603 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175602 91177308-0d34-0410-b5e6-96231b3b80d8
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and removing instructions. The implementation seems more complicated than it
needs to be, but I couldn't find something simpler that dealt with all of the
corner cases.
Also add a call to repairIndexesInRange() from repairIntervalsInRange().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175601 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175600 91177308-0d34-0410-b5e6-96231b3b80d8
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assertions in the register allocator when running 'make check' without
LiveVariables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175599 91177308-0d34-0410-b5e6-96231b3b80d8
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after the two-address pass. The remaining problems in 'make check' are occurring
later.
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Code review feedback on r175580 from Jordan Rose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175595 91177308-0d34-0410-b5e6-96231b3b80d8
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SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.
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This is for the sandboxed llvm translator. Rough estimate,
from companion test:
https://codereview.chromium.org/12218141/
"""
Pruned out approx 35099 bytes worth of MCAsmParser symbols
Pruned out approx 49935 bytes worth of ::AsmParser symbols
Pruned out approx 183308 bytes worth of ARMAsmParser symbols
Pruned out approx 54552 bytes worth of X86AsmParser symbols
Pruned out approx 11415 bytes worth of ELFAsmParser symbols
Pruned out approx 7253 bytes worth of COFFAsmParser symbols
Pruned out approx 18450 bytes worth of DarwinAsmParser symbols
Pruned out approx 403 bytes worth of MCAsmLexer symbols
Pruned out approx 7009 bytes worth of ::AsmLexer symbols
Pruned out approx 359436 bytes worth of MatchTable symbols
"""
BUG= https://code.google.com/p/nativeclient/issues/detail?id=1222
Review URL: https://codereview.chromium.org/12218139
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175584 91177308-0d34-0410-b5e6-96231b3b80d8
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This generalizes Optional to require less from the T type by using aligned
storage for backing & placement new/deleting the T into it when necessary.
Also includes unit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175580 91177308-0d34-0410-b5e6-96231b3b80d8
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require call cpp file anyway, so we wouldn't gain anything by keeping them
inline.
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declarations that set the attribute groups, so we must do it on our own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175577 91177308-0d34-0410-b5e6-96231b3b80d8
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MS-style inline assembly.
This is a follow-on to r175334. Forcing a FP to be emitted doesn't ensure it
will be used. Therefore, force the base pointer as well. We now treat MS
inline assembly in the same way we treat functions with dynamic stack
realignment and VLAs. This guarantees the BP will be used to reference
parameters and locals.
rdar://13218191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175576 91177308-0d34-0410-b5e6-96231b3b80d8
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R=jvoung@chromium.org,eliben@chromium.org
BUG=
Review URL: https://codereview.chromium.org/12302030
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which uses it. This is not ideal, but it ought to at least restore the
behavior to what it was before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175571 91177308-0d34-0410-b5e6-96231b3b80d8
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excluding visibility bits.
Mips (o32 abi) specific e_header setting.
EF_MIPS_ABI_O32 needs to be set in the
ELF header flags for o32 abi output.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175569 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175568 91177308-0d34-0410-b5e6-96231b3b80d8
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excluding visibility bits.
Mips (Mips16) specific e_header setting.
EF_MIPS_ARCH_ASE_M16 needs to be set in the
ELF header flags for Mips16.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175566 91177308-0d34-0410-b5e6-96231b3b80d8
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excluding visibility bits.
Mips (MicroMips) specific STO handling .
The st_other field settig for STO_MIPS_MICROMIPS
Contributer: Zoran Jovanovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175564 91177308-0d34-0410-b5e6-96231b3b80d8
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excluding visibility bits.
Generic STO handling at the Target level.
The st_other field of the ELF symbol table is one
byte in size. The first 2 bytes are used for generic
visibility and are currently handled by llvm.
The other six bits are processor specific and need
to be set at the target level.
A couple of notes:
The new static methods for accessing and setting the "other"
flags in include/llvm/MC/MCELF.h match the style guide
and not the other methods in the file. I don't like the
inconsistency, but feel I should follow the prescribed
lowerUpper() convention.
STO_ value definitions are not specified in gnu land as
consistently as the STT_ and STB_ fields. Probably because
the latter were defined in a standards doc and the former
defined partially in code. I have stuck with the full byte
definition of the flags.
Contributer: Zoran Jovanovic
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In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."
I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.
radar://13191881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175555 91177308-0d34-0410-b5e6-96231b3b80d8
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considered as instructions with side effects.
rdar://13227456
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so we cant deref it.
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character devices.
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/dev/stdin as an input when stdin is connected to a tty, for example.
No test, because it's difficult to write a reasonably portable test
for this. /dev/stdin isn't a character device when stdin is redirected
from a file or connected to a pipe.
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When creating an allocation hint for a register pair, make sure the hint
for the physical register reference is still in the allocation order.
rdar://13240556
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Target implementations of getRegAllocationHints() should use the
provided allocation order, and they can never return hints outside the
order. This is already documented in TargetRegisterInfo.h.
<rdar://problem/13240556>
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unit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175538 91177308-0d34-0410-b5e6-96231b3b80d8
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