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Test case by llvm-stress.
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and add the cost of extracting values from the roots of the tree.
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For when 16 TB just isn't enough.
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This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
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64-bit code models need multiple relocations that can't be inferred from
the opcode like they can in 32-bit code.
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Constant pool entries are accessed exactly the same way as global
variables.
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This fixes the pic32 code model for SPARC v9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179469 91177308-0d34-0410-b5e6-96231b3b80d8
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SDNodes and MachineOperands get target flags representing the %hi() and
%lo() assembly annotations that eventually become relocations.
Also define flags to be used by the 64-bit code models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179468 91177308-0d34-0410-b5e6-96231b3b80d8
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Leaving MFCR has having unmodeled side effects is not enough to prevent
unwanted instruction reordering post-RA. We could probably apply a stronger
barrier attribute, but there is a better way: Add all (not just the first) CR
to be spilled as live-in to the entry block, and add all CRs to the MFCR
instruction as implicitly killed.
Unfortunately, I don't have a small test case.
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Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.
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It doesn't seem like anybody is checking types this late in isel, so no
test case.
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There is a Constant with non-constant operands: blockaddress.
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This is basically the same fix in three different places. We use a set to avoid
walking the whole tree of a big ConstantExprs multiple times.
For example: (select cmp, (add big_expr 1), (add big_expr 2))
We don't want to visit big_expr twice here, it may consist of thousands of
nodes.
The testcase exercises this by creating an insanely large ConstantExprs out of
a loop. It's questionable if the optimizer should ever create those, but this
can be triggered with real C code. Fixes PR15714.
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For functions that need to spill CRs, and have dynamic stack allocations, the
value of the SP during the restore is not what it was during the save, and so
we need to use the FP in these cases (as for all of the other spills and
restores, but the CR restore has a special code path because its reserved slot,
like the link register, is specified directly relative to the adjusted SP).
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The order of copies depends on queue order, which is not very stable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179455 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179453 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179452 91177308-0d34-0410-b5e6-96231b3b80d8
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to check for a variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179451 91177308-0d34-0410-b5e6-96231b3b80d8
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The initial values were arbitrary. I want them to be more
conservative. This represents the number of latency cycles hidden by
OOO execution. In practice, I think it should be within a small factor
of the complex floating point operation latency so the scheduler can
make some attempt to hide latency even for smallish blocks.
These are by no means the best values, just a starting point for
tuning heuristics. Some benchmarks such as TSVC run faster with this
lower value for SandyBridge. I haven't run anything on Haswell, but
it's shouldn't be 2x SB.
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The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.
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I need to handle this for the test case in my following scheduler
commit.
Work is already under way to redesign the mechanism for node order
propagation because this case by case approach is unmaintainable.
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I hope this brings http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32 back.
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lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.
No functionality changes.
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Should fix the bots.
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We are now able to handle big endian macho files in llvm-readobject. Thanks to
David Fang for providing the object files.
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change intended. Test case previously added in r178568.
Part of rdar://13611297
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instructions.
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Fixes PR15737.
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perform a preliminary traversal of the graph to collect values with multiple users and check where the users came from.
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from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles.
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patch by Veselov, Yuri <Yuri.Veselov@intel.com>.
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when parsing MS-style inline assembly. No functional change intended.
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Previously it was just instruction attachments.
Depends on a driver change to actually work:
https://codereview.chromium.org/14072004/
BUG= http://code.google.com/p/nativeclient/issues/detail?id=3348
Review URL: https://codereview.chromium.org/14022009
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extend the ABI checker to verify.
Also promote weak symbols to internal ones, which was required because the scons barebones tests define weak versions of memcpy/memset
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3339
TEST= llvm-regression (globalcleanup.ll), scons barebones tests
Review URL: https://codereview.chromium.org/13989005
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BUG=https://code.google.com/p/nativeclient/issues/detail?id=3337
TEST=test/NaCl/PNaClABI/*.ll
Review URL: https://codereview.chromium.org/13932023
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This doesn't disallow the va_start/va_end/va_copy intrinsics yet;
these will get disallowed later when we add whitelisting of intrinsics
to the PNaCl ABI checker.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3338
TEST=test/NaCl/PNaClABI/*.ll
Review URL: https://codereview.chromium.org/13884013
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is a follow on to r179393 and r179399. Test case to be added on
the clang side.
Part of rdar://13453209
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The first release of the stable PNaCl ABI won't support zero-cost C++
exception handling.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3377
TEST=toolchain trybots + gcc torture tests + Spec2k + LLVM regression tests
Review URL: https://codereview.chromium.org/14044006
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the source test root.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179401 91177308-0d34-0410-b5e6-96231b3b80d8
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is a follow on to r179393. Test case to be added on the clang side.
Part of rdar://13453209
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