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2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19refactor the struct byte swapping to a helper function.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179851 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Only run the tests in test/Object/ARM if we have ARM support.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179850 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Attributes: Don't print trailing whitespace on the function attribute comment.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Don't read one command past the end.Rafael Espindola
Thanks to Evgeniy Stepanov for reporting this. It might be a good idea to add a command iterator abstraction to MachO.h, but this fixes the bug for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Revert 179826. Tests were worthless.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Revert "PR14606: debug info imported_module support"Eric Christopher
This reverts commit r179836 as it seems to have caused test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19PR14606: debug info imported_module supportDavid Blaikie
Adding another CU-wide list, in this case of imported_modules (since they should be relatively rare, it seemed better to add a list where each element had a "context" value, rather than add a (usually empty) list to every scope). This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll need to expand this to cover DW_TAG_imported_declaration too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Add support for index resources (for a SlotIndex) to be relinquished.Lang Hames
When the SlotIndexes pass was introduced it was intended to support insertion of code during register allocation. Removal of code was a minor consideration (and raised the question of what to do about dangling SlotIndex objects pointing to the erased index), so I opted to keep all indexes around indefinitely and simply null out those that weren't being used. Nowadays people are moving more code around (e.g. via HandleMove), which means more zombie indexes. I want to start killing off indexes when we're done with them to reclaim the resources they use up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use 'array_lengthof' as possible to avoid magic numbersMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard
InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Reorganize lit tests and document how they should be organizedTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Keep coding stanard. Don't use "else if" after "return".Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Don't run expensive -O2 and -O3 in tests.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering functionEli Bendersky
arguments in entry BBs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use an enum instead of magic constants to improve readability.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement a better fix for PR15185.Bill Wendling
If the return type is a pointer and the call returns an integer, then do the inttoptr convertions. And vice versa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179817 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Relax this assert. It may not hold in all cases.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier
AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Assert if we're trying to generate a null compact unwind entry.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Set the compact unwind encoding to 'requires EH DWARF' if we cannot generate ↵Bill Wendling
a CU encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Disable PPC comparison optimization by defaultHal Finkel
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do I'm disabling this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement optimizeCompareInstr for PPCHal Finkel
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Make the TargetIndependent flag have the right boolean value.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer
available. This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix typoEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Cleanup patch:Bill Wendling
Semantics of parameters named Index and Idx were inconsistent between "include/llvm/IR/Attributes.h", "lib/IR/AttributeImpl.h" and "lib/IR/Attributes.cpp": sometimes these were fixed 1-based indexes of IR parameters (or AttributeSet::ReturnIndex for IR return values or AttributeSet::FunctionIndex for IR functions), other times they were the internal slot for storage in the underlying AttributeSetImpl. I renamed usage of the former to "Index" and usage of the latter to "Slot" ("Slot" was already being used consistently for the latter in a subset of cases) Patch by Stephen Lin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179791 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18This patch addresses two cleanup issues:Bill Wendling
1. Verify::VerifyParameterAttrs in "lib/IR/Verifier.cpp" and AttrBuilder::removeFunctionOnlyAttrs in "lib/IR/Attributes.cpp" (only called by Verify::VerifyFunctionAttrs) separately maintained a list of function-only attribute types. I've consolidated the logic into a new function used for both cases in "lib/IR/Verifier.cpp", so this logic is in one place (other than the AsmParser front-end) 2. Various functions in "lib/IR/Verifier.cpp" passed AttributeSet around by reference needlessly, as it's just a handle to an immutable pimpl body. Patch by Stephen Lin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix a -Wdocumentation warningDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18In the function InstCombiner::visitExtractElementInst() removed the ↵Anat Shemer
limitation that extract is promoted over a cast only if the cast has only one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18C API: Fix coding styleTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Added a function scalarizePHI() that sclarizes a vector phi instruction if ↵Anat Shemer
it has only 2 uses: one to promote the vector phi in a loop and the other use is an extract operation of one element at a constant location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix comment. Patch by Stephen Lin.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18At Jim Grosbach's request detemplate Object/MachO.h.Rafael Espindola
We are still able to handle mixed endian objects by swapping one struct at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix a comment, PR15777.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Allow misaligned stores in x86 fast-isel.Derek Schuff
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18LoopVectorizer: Recognize min/max reductionsArnold Schwaighofer
A min/max operation is represented by a select(cmp(lt/le/gt/ge, X, Y), X, Y) sequence in LLVM. If we see such a sequence we can treat it just as any other commutative binary instruction and reduce it. This appears to help bzip2 by about 1.5% on an imac12,2. radar://12960601 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix CMake buildDerek Schuff
Clean up the LLVMBuild and CMakeLists.txt files BUG=none TEST=none Review URL: https://codereview.chromium.org/14328017
2013-04-18Fix grammar in LLVMBuild.rstEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Simplify some logic and add a FIXME for unhandled unary minus.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Make this private method.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fixes to LangRef.rst: incorrect attributes syntax and misplaced 'nobuiltin'Eli Bendersky
Patch by Stephen Lin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179763 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix comment spacing.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18LoopVectorize: Use a set to avoid longer cycles in the reduction chain too.Benjamin Kramer
Fixes PR15748. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix for PR14824, An ARM Load/Store Optimization bugHao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Revert "Combine bit test + conditional or into simple math"David Majnemer
It is causing stage2 builds to fail, let's get them running again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Combine bit test + conditional or into simple mathDavid Majnemer
Simplify: (select (icmp eq (and X, C1), 0), Y, (or Y, C2)) Into: (or (shl (and X, C1), C3), y) Where: C3 = Log(C2) - Log(C1) If: C1 and C2 are both powers of two git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179748 91177308-0d34-0410-b5e6-96231b3b80d8
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