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2012-07-10 Mips specific inline asm operand modifier 'L'.Jack Carter
Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen
It will surely be needed by heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth
generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Run early if-conversion in domtree post-order.Jakob Stoklund Olesen
This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier
X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add newline.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add test case accidentally omitted from r160002.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth
back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem
multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Reverse assembler/disassembler operand order for gather instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth
quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth
of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10ARM: Allow more flexible patterns in NEON formats.Jim Grosbach
Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Allow intrinsics to be used in place of node matchables.Jim Grosbach
TableGen has support for using an intrinics name directly in a DAG, but this breaks down when referring to just a node, as that's handled initializer list stuff entirely via subclassing in the parser. That is, using an instrinsic like "(int_my_intrinsic ...)" works fine. Using it standalone for parameterizing the operator in such a DAG does not. Fixing this is simple enough, as we simply declare Intrinsic as deriving from SDPatternOperator, which is the class name intended for exactly this purpose in TargetSelectionDAG.td. When the intrinsic is actually used in the DAG pattern, it will be recognized and expanded to an intrinsic_wo_chain (et. al.) just like when it's used directly. Incoming ARM NEON cleanup based on this and a bit of functionality improvement after that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Delete code for folding undefs in ScalarEvolution. It's invalid inDan Gohman
obscure ways, and it isn't actually important in the real world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Revert r159938 (and r159945) to appease the buildbots.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Machine model: allow itineraries to be shared by different processor models.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09indentationAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson
move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Reapply r158846.Akira Hatanaka
Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09instcombine: merge the functions that remove dead allocas and dead ↵Nuno Lopes
mallocs/callocs/... This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :) In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Some formatting to keep Clang happyRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Oops - correct broken disassembly for VMOVRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Spelling!Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton
three-register dp instructions where permissable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-08Remove some trivial copy ctors so the classes become trivially copyable and ↵Benjamin Kramer
get the optimized SmallVector implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-08SmallVector: Make use of move semantics to speed up moving objects in ↵Benjamin Kramer
erase() and insert() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Tweak spelling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07X86: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07LLVMConfig.cmake.in: Quote around @LLVM_INSTALL_PREFIX@, or it would not ↵NAKAMURA Takumi
accept whitespace paths. Thanks to Kai. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159887 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Use the DebugInfo wrappers instead of mucking about with the MDNode directly.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Print the name last.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier
should be camel case, and start with a lower case letter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06teach instcombine to remove allocated buffers even if there are stores, ↵Nuno Lopes
memcpy/memmove/memset, and objectsize users. This means we can do cheap DSE for heap memory. Nothing is done if the pointer excapes or has a load. The churn in the tests is mostly due to objectsize, since we want to make sure we don't delete the malloc call before evaluating the objectsize (otherwise it becomes -1/0) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Since SmallMap was removed in r158644, remove documentation in ↵Dmitri Gribenko
ProgrammersManual.html. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Check if it's a scope last, because several things are scopes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06ARM: Add test cleanup entry to the README.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06revert r159851.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Reapply r158846.Akira Hatanaka
Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Add a print method to the ObjC property object.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Remove trailing comma in array initialization list.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Remove unnecessary 'llvm::'.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159842 91177308-0d34-0410-b5e6-96231b3b80d8
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