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2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as ↵Tom Stellard
conditional operator..." This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in ↵Tom Stellard
nonreturn function, instead of assert(0)." This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard
This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16make ConstantRange::getSetSize() properly compute the size of wrapped and ↵Nuno Lopes
full sets. Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16With r160248 in place this code is no longer needed.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] a bit more refactoring, addressed some of the style comments from ↵Kostya Serebryany
chandlerc, partially implemented crash callback merging (under flag) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16MSVC's implementation of isalnum will assert on characters > 255, so we need ↵Aaron Ballman
to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] refactor instrumentation to allow merging the crash callbacks (not ↵Kostya Serebryany
fully implemented yet, no functionality change except the BB order) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn ↵NAKAMURA Takumi
function, instead of assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ↵NAKAMURA Takumi
operator... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Doubleword Shift Left Logical Plus 32Jack Carter
Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵NAKAMURA Takumi
AMDGPUCommonTableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ↵NAKAMURA Takumi
and <llvm/TypeBuilder.h> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix tests that failed on i686-win32 after r160248:Alexey Samsonov
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp. 2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of vector add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16test/CodeGen/R600: Add some basic tests v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Build script changes for R600/SI Codegen v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16include/llvm: Add R600 Intrinsics v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] initialize asan error callbacks in runOnModule instead of doing that ↵Kostya Serebryany
on-demand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem
undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert r160254 temporarily.Chandler Carruth
It turns out that ASan relied on the at-the-end block insertion order to (purely by happenstance) disable some LLVM optimizations, which in turn start firing when the ordering is made more "normal". These optimizations in turn merge many of the instrumentation reporting calls which breaks the return address based error reporting in ASan. We're looking at several different options for fixing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Teach AddressSanitizer to create basic blocks in a more natural order.Chandler Carruth
This is particularly useful to the backend code generators which try to process things in the incoming function order. Also, cleanup some uses of IRBuilder to be a bit simpler and more clear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add a basic test for AddressSanitizer. This is just a bare-bonesChandler Carruth
functionality test. In general, unless the functionality is substantially separated, we should lump more basic testing into this file. The test running infrastructure likes having a few test files with more comprehensive testing within them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160253 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add support for attaching branch weight metadata directly from the IRBuilder.Chandler Carruth
Added a basic unit test for this with CreateCondBr. I didn't go all the way and test the switch side as the boilerplate for setting up the switch IRBuilder unit tests is a lot more. Fortunately, the two share all the interesting code paths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.Chandler Carruth
This is in anticipation of changing CreateCondBr and wanting to test those changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Move the IRBuilder unittest from Support to VMCore. This got missed inChandler Carruth
the original move of IRBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160249 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16This CL changes the function prologue and epilogue emitted on X86 when stack ↵Alexey Samsonov
needs realignment. It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completesChandler Carruth
the move of *Builder classes into the Core library. No uses of this builder in Clang or DragonEgg I could find. If there is a desire to have an IR-building-support library that contains all of these builders, that can be easily added, but currently it seems likely that these add no real overhead to VMCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Update the header guard I missed when moving the header.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160242 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Move llvm/Support/MDBuilder.h to llvm/MDBuilder.h, to live withChandler Carruth
IRBuilder, DIBuilder, etc. This is the proper layering as MDBuilder can't be used (or implemented) without the Core Metadata representation. Patches to Clang and Dragonegg coming up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be ↵Nadav Rotem
wider than the output element type. Make sure to trunc them if needed. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15llvm/test/CodeGen/X86/2012-07-15-broadcastfold.ll: Rewrite expressions to ↵NAKAMURA Takumi
fit various targets. - Make sure existence of "barrier". - Confirm reload corresponding to spill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot. PR12782. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Refactor the code that checks that all operands of a node are UNDEFs.Nadav Rotem
Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs. Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160229 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth
The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Move IsSameValue from clang's ASTImporter to be methods on theEric Christopher
APInt/APSInt classes. Part of rdar://11875995 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-14AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ↵Nadav Rotem
vector with the same element type as the input vector. This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-14Add a dagcombine optimization to convert concat_vectors of undefs into a ↵Nadav Rotem
single undef. The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-14Account for early-clobber reload instructions.Jakob Stoklund Olesen
No test case, there are no in-tree targets that require this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160219 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Be more verbose when detecting dominance problems.Jakob Stoklund Olesen
Catch uses of undefined physregs that haven't been added to basic block live-in lists. Run the verifier to pinpoint the problem. Also run the verifier when a virtual register use is not jointly dominated by defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13LSR Fix: check SCEV expression safety before expansion.Andrew Trick
All SCEV expressions used by LSR formulae must be safe to expand. i.e. they may not contain UDiv unless we can prove nonzero denominator. Fixes PR11356: LSR hoists UDiv. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13IVUsers should only generate SCEV's for values that are safe to speculate.Andrew Trick
This allows SCEVExpander to run on the IV expressions. This codifies an assumption made by LSR to complete the fix for PR11356, but I haven't been able to generate a separate unit test for this part. I'm adding it as an extra safety check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Factor SCEV traversal code so I can use it elsewhere. No functionality.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13This is one of the first steps at moving to replace target-dependent Joel Jones
intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Revert r160194, which switched to use LV information for finding localChandler Carruth
kills. This is causing miscompiles that I'm working on tracking down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth
removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Fixed few warnings.Galina Kistanova
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen
Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
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