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2006-05-01Remove previous patch, which wasn't quite right.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01instructions can be in different namespaces. Make sure to use the rightChris Lattner
one for each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28038 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Put PHI/INLINEASM into the correct namespace.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28037 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01FormatingEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28036 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Dis-favor stores moreEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Bottom up register-pressure reduction scheduler now pushes store operationsEvan Cheng
up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Mark instructions whose pattern is (store ...) isStore.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28032 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Didn't mean ScheduleDAGList.cpp to make the last checkin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng
performance regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Intel mode no longer uses %'s on registersChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Remove %'s from register names when in intel mode.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28027 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01Format #APP lines a bit nicerChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-30Local spiller kills a store if the folded restore is turned into a copy.Evan Cheng
But this is incorrect if the spilled value live range extends beyond the current BB. It is currently controlled by a temporary option -spiller-check-liveout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-29Mingw32 patches supplied by Anton Korobeynikov.Jeff Cohen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28023 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Remove a bogus transformation. This fixes ↵Chris Lattner
SingleSource/UnitTests/2006-01-23-InitializedBitField.c with some changes I have to the new CFE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28I can't spell: Register, not Regsiter.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28021 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Implemented x86 inline asm b, h, w, k modifiers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28020 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Fix InstCombine/2006-04-28-ShiftShiftLongLong.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28019 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28new testcase miscompiled by instcombineChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28018 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28testcase that crashes the ppc backend, which can't sextinreg(i1)Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28016 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Initial caller side support (for CCC only, not FastCC) of 128-bit vectorEvan Cheng
passing by value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Bare-bone X86 inline asm printer support.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28014 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Update. It should use two shufps, not three!Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28013 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Remove the temporary option: -no-isel-fold-inflightEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Implement four-wide shuffle with 2 shufps if no more than two elements comeEvan Cheng
from each vector. e.g. shuffle(G1, G2, 7, 1, 5, 2) ==> movaps _G2, %xmm0 shufps $151, _G1, %xmm0 shufps $216, %xmm0, %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Fix PR743: emit -help output of a tool to cout, not cerr.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28010 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28TargetLowering::LowerArguments should return a VBIT_CONVERT ofEvan Cheng
FORMAL_ARGUMENTS SDOperand in the return result vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Mapping of physregs can make it so that the designated and input physregs areChris Lattner
the same. In this case, don't emit a noop copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Fix Transforms/Reassociate/2006-04-27-ReassociateVector.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28007 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28new testcaseChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28006 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Use movaps instead of movapd for spill / restore.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28005 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Added a temporary option -no-isel-fold-inflight to control whether a "inflight"Evan Cheng
node can be folded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28When isel'ing a node, mark its operands "InFlight" before selecting them. TheseEvan Cheng
nodes should not be folded into other nodes. This fixes the miscompilation of PR 749. Temporarily under flag control. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28002 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28When we have a two-address instruction where the input cannot be clobberedChris Lattner
and is already available, instead of falling back to emitting a load, fall back to emitting a reg-reg copy. This generates significantly better code for some SSE testcases, as SSE has lots of two-address instructions and none of them are read/modify/write. As one example, this change does: pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255 xorps %XMM2, %XMM5 cmpltps %XMM1, %XMM0 - movaps XMMWORD PTR [%ESP + 52], %XMM0 - movapd %XMM6, XMMWORD PTR [%ESP + 52] + movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 68] movapd XMMWORD PTR [%ESP + 52], %XMM6 movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 36] cmpltps %XMM3, %XMM0 - movaps XMMWORD PTR [%ESP + 20], %XMM0 - movapd %XMM7, XMMWORD PTR [%ESP + 20] + movaps %XMM7, %XMM0 cmpltps %XMM7, XMMWORD PTR [%ESP + 4] movapd XMMWORD PTR [%ESP + 20], %XMM7 cmpltps %XMM4, %XMM0 ... which is far better than a store followed by a load! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Test case for PR748Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28000 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28Add a noteChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27999 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Add a noteChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27998 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Add support for inserting undef into a vector. This implementsChris Lattner
Transforms/InstCombine/vec_insert_to_shuffle.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27997 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27This should turn into one vector shuffle instruction.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27996 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Make x86 isel lowering produce tailcall nodes. They are match to normal callsEvan Cheng
for now. Patch contributed by Alexander Friedman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27A couple of new entries.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27993 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Support for passing 128-bit vector arguments via XMM registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27992 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector usesEvan Cheng
(VAND, VADD, etc.). Legalizer will assert otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27For PR747:Reid Spencer
If we fail to find a required program, simply set that program to echo out something that tells the user the situation. That is, instead of just "true runtest" we now get "echo 'Skipped: runtest not found'". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27990 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27OopsEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27989 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Bug fix: not updating NumIntRegs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27988 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll andChris Lattner
PR748. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27987 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27new testcaseChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27986 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27- Clean up formal argument lowering code. Prepare for vector pass by value work.Evan Cheng
- Fixed vararg support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
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