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2011-03-11Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-1180 columnsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach
effect that we get proper instruction printing using the "pop" mnemonic for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Roll r127459 back in:Cameron Zwarich
Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Fix the GCC test suite issue exposed by r127477, which was caused by stackCameron Zwarich
protector insertion not working correctly with unreachable code. Since that revision was rolled out, this test doesn't actual fail before this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach FastISel to support register-immediate-immediate instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-1180 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach
as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach
and VDUPLN32d, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach
as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11This FIXME has been fixed.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Properly pseudo-ize ARM MVNCCi.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach
the diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove optimization emitting a reference insted of label difference, since ↵Jan Sjödin
it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar
created from the", it broke some GCC test suite tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Force re-linking of LLVMgold.so when its exports file changes.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Fix processing of gold.exports.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11While printing annotations, print line number and variable name if debug ↵Devang Patel
info is present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Replace -dag-chain-limit flag with constant. It has survived a release cycle ↵Andrew Trick
without being touched, so no longer needs to pollute the hidden-help text. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Add LTO and gold plugin to the CMake build. Linux-only, support forOscar Fuentes
other systems pending. PR9456. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ComputeMaskedBits: sub falls through to add, and sub doesn't have the same ↵Benjamin Kramer
overflow semantics as add. Should fix the selfhost failures that started with r127463. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11InstCombine: Fix a thinko where transform an icmp under the assumption that ↵Benjamin Kramer
it's a zero comparison when it's not. Fixes PR9454. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach ComputeMaskedBits about nsw on add. I don't think there's anything we canNick Lewycky
do with nuw here, but sub and mul should be given similar treatment. Fixes PR9343 #15! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Fix use of CompEnd predicate to be standards conformingJohn Wiegley
The existing CompEnd predicate does not define a strict weak order as required by the C++03 standard; therefore, its use as a predicate to std::upper_bound is invalid. For a discussion of this issue, see http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270 This patch replaces the asymmetrical comparison with an iterator adaptor that achieves the same effect while being strictly standard-conforming by ensuring an apples-to-apples comparison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach TableGen to pre-calculate register enum values when creating theJim Grosbach
CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11silence a conditional assignment -Wuninitialized warning.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Make the register enum value part of the CodeGenRegister struct.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Change the x86 32-bit scheduler to register pressure and fix up theEric Christopher
corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng
the load is indexed. rdar://9117613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10RecursivelyDeleteTriviallyDeadInstructions only needs aDan Gohman
Value, not an Instruction, so casting is not necessary. Also, it's theoretically possible that the Value is not an Instruction, since WeakVH follows RAUWs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Don't compute the file size if we don't need to.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Fix reassociate to postpone certain instruction deletions untilDan Gohman
after it has finished all of its reassociations, because its habit of unlinking operands and holding them in a datastructure while working means that it's not easy to determine when an instruction is really dead until after all its regular work is done. rdar://9096268. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10DMB can just be a pat referencing MCR.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Reorganize a bit. No functional change, just moving patterns up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Pseudo-instructions are codegenonly by definition.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Memory barrier instructions don't need special handling in tblgen anymore.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it ↵Benjamin Kramer
cannot overflow. This happens a lot in clang-compiled C++ code because it adds overflow checks to operator new[]: unsigned *foo(unsigned n) { return new unsigned[n]; } We can optimize away the overflow check on 64 bit targets because (uint64_t)n*4 cannot overflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Add r127409 back now that the windows file was updated.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Try to fix the windows build.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Revert r127409 which broke all the Windows bots.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127413 91177308-0d34-0410-b5e6-96231b3b80d8
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