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2010-08-11llvm-mc: Add -show-inst-operands, for dumping the parsed instruction ↵Daniel Dunbar
representation before matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Really control isel of barrier instructions with cpu feature.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng
instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11- Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng
memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Switch to using the generated match functions instead of stub ↵Daniel Dunbar
implementations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ARM: Mark some disassembler only instructions as not available for matching --Daniel Dunbar
for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ARM: Quote $p in an asm string.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only ↵Daniel Dunbar
warning, for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Improve indentation.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Remove AVX 256-bit cast intrinsics now that clang is using ↵Bruno Cardoso Lopes
__builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Remove AVX 256-bit unpack and interleave intrinsics now that clang is using ↵Bruno Cardoso Lopes
__builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Remove AVX 256-bit shuffle intrinsics now that clang is using ↵Bruno Cardoso Lopes
__builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Update test to match output of optimize compares for ARM.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11CMake: corrections on LLVM.cmake external services.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110763 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Mark ARM compare instructions as isCompare.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Make it possible to set the cpu used for codegen.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11When analyzing loop exit conditions combined with and and or, don'tDan Gohman
make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11lto: Fix an inverted conditional which prevented the addition of symbols scrapedDaniel Dunbar
from inline assembly, except in cases where they had already been seen (in which case they would get added twice). - I can't see how this ever worked... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11lto: Fix gratuitous memory leaks.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add a separate ARM instruction format for Saturate instructions.Bob Wilson
(I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Avoid multiple definition warnings when both config.h andOscar Fuentes
llvm-config.h are included. This is the cmake counterpart of r110547. See bug #7809. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10lto: Reduce nesting.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10LTOModule.cpp: Fix numerous style issues.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Rename and reorder the arguments to isImpliedCond, for consistency and clarity.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10We already have this as OperandNode.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10CBZ and CBNZ are implemented.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add AVX matching patterns to Packed Bit Test intrinsics.Bruno Cardoso Lopes
Apply the same approach of SSE4.1 ptest intrinsics but create a new x86 node "testp" since AVX introduces vtest{ps}{pd} instructions which set ZF and CF depending on sign bit AND and ANDN of packed floating-point sources. This is slightly different from what the "ptest" does. Tests comming with the other 256 intrinsics tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Now that we're using ConstantRange to represent potential values, make use ↵Owen Anderson
of that represenation to create constraints from comparisons other than eq/neq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10The optimize comparisons pass removes the "cmp" instruction this is checking ↵Bill Wendling
for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add test for recent instcombine vector shuffle enhancementNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10upgrade to use new intrinsics, patch by Dan Hipschman!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add the minimal amount of smarts necessary to instcombine of shufflevectors ↵Nate Begeman
to recognize patterns generated by clang for transpose of a matrix in generic vectors. This is made of two parts: 1) Propagating vector extracts of hi/lo half into their users 2) Recognizing an insertion of even elements followed by the odd elements as an unpack. Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Turn optimize compares back on with fix. We needed to test that a machine op wasBill Wendling
a register before checking if it was defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Give up on register class recalculation when the register is used with subregJakob Stoklund Olesen
operands. We don't currently have a hook to provide "the largest super class of A where all registers' getSubReg(subidx) is valid and in B". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Revert r110718; it broke clang-i386-darwin9.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Avoid editing the current live interval during remat.Jakob Stoklund Olesen
The live interval may be used for a spill slot as well, and that spill slot could be shared by split registers. We cannot shrink it, even if we know the current register won't need the spill slot in that range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10More debug spewJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Turn optimize cmps on by default so that we can get some testing by the nightlyBill Wendling
ARM testers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add missing argument. CreateCompositeTypeEx() users, please verify.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Switch over to using ConstantRange to track integral values.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Do not forget debug info for enums. Use named mdnode to keep track of these ↵Devang Patel
types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10tests: Don't error out if HOME isn't present in t the environment.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Delete some unused instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng
function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Make it possible to set the flags passed to the assembler.Rafael Espindola
Nick, please review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110705 91177308-0d34-0410-b5e6-96231b3b80d8
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