1 files changed, 9 insertions, 9 deletions
diff --git a/test/NaCl/ARM/neon-vstlane-sandboxing.ll b/test/NaCl/ARM/neon-vstlane-sandboxing.ll
index 769a7c6712..d8a004b6af 100644
--- a/test/NaCl/ARM/neon-vstlane-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vstlane-sandboxing.ll
@@ -15,7 +15,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
   %tmp2 = extractelement <4 x i16> %tmp1, i32 2
   store i16 %tmp2, i16* %A, align 8
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst1.16 {d{{[0-9]+}}[2]}, [r0, :16]
+; CHECK-NEXT:    vst1.16 {d{{[0-9]+}}[2]}, [r0:16]
   ret void
 }
 
@@ -24,7 +24,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
   %tmp2 = extractelement <2 x i32> %tmp1, i32 1
   store i32 %tmp2, i32* %A, align 8
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst1.32 {d{{[0-9]+}}[1]}, [r0, :32]
+; CHECK-NEXT:    vst1.32 {d{{[0-9]+}}[1]}, [r0:32]
   ret void
 }
 
@@ -46,7 +46,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
   %tmp2 = extractelement <8 x i16> %tmp1, i32 5
   store i16 %tmp2, i16* %A, align 8
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst1.16 {d{{[0-9]+}}[1]}, [r0, :16]
+; CHECK-NEXT:    vst1.16 {d{{[0-9]+}}[1]}, [r0:16]
   ret void
 }
 
@@ -54,7 +54,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
   %tmp1 = load <8 x i8>* %B
   call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst2.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0, :16]
+; CHECK-NEXT:    vst2.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:16]
   ret void
 }
 
@@ -63,7 +63,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
   %tmp1 = load <4 x i16>* %B
   call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0, :32]
+; CHECK-NEXT:    vst2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:32]
   ret void
 }
 
@@ -94,7 +94,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 ; CHECK-NEXT:    vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
   call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst2.32 {d{{[0-9]+}}[0], d{{[0-9]+}}[0]}, [r0, :64]
+; CHECK-NEXT:    vst2.32 {d{{[0-9]+}}[0], d{{[0-9]+}}[0]}, [r0:64]
   ret void
 }
 
@@ -128,7 +128,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
   %tmp1 = load <8 x i8>* %B
   call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst4.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0, :32]
+; CHECK-NEXT:    vst4.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:32]
   ret void
 }
 
@@ -146,7 +146,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
   %tmp1 = load <2 x i32>* %B
   call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst4.32 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0, :128]
+; CHECK-NEXT:    vst4.32 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:128]
   ret void
 }
 
@@ -157,7 +157,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 ; CHECK-NEXT:    vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
   call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
 ; CHECK:         bic r0, r0, #3221225472
-; CHECK-NEXT:    vst4.16 {d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0-9]+}}[3]}, [r0, :64]
+; CHECK-NEXT:    vst4.16 {d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0-9]+}}[3]}, [r0:64]
   ret void
 }