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-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td199
1 files changed, 0 insertions, 199 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index ca5e7e1dd5..0f53383e52 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -14,205 +14,6 @@
include "PowerPCInstrFormats.td"
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Constraint definitions.
-//
-// Note that the semantics of these constraints are hard coded into tblgen. To
-// modify or add constraints, you have to hack tblgen.
-//
-
-class SDTypeConstraint<int opnum> {
- int OperandNum = opnum;
-}
-
-// SDTCisVT - The specified operand has exactly this VT.
-class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
- ValueType VT = vt;
-}
-
-// SDTCisInt - The specified operand is has integer type.
-class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisFP - The specified operand is has floating point type.
-class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisSameAs - The two specified operands have identical types.
-class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
- int OtherOperandNum = OtherOp;
-}
-
-// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
-// smaller than the 'Other' operand.
-class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
- int OtherOperandNum = OtherOp;
-}
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Profile definitions.
-//
-// These use the constraints defined above to describe the type requirements of
-// the various nodes. These are not hard coded into tblgen, allowing targets to
-// add their own if needed.
-//
-
-// SDTypeProfile - This profile describes the type requirements of a Selection
-// DAG node.
-class SDTypeProfile<int numresults, int numoperands,
- list<SDTypeConstraint> constraints> {
- int NumResults = numresults;
- int NumOperands = numoperands;
- list<SDTypeConstraint> Constraints = constraints;
-}
-
-// Builtin profiles.
-def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
-def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
-def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
- SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
-]>;
-def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
- SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
-]>;
-def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
- SDTCisSameAs<0, 1>, SDTCisInt<0>
-]>;
-def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
- SDTCisSameAs<0, 1>, SDTCisFP<0>
-]>;
-def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
- SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
- SDTCisVTSmallerThanOp<2, 1>
-]>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node Properties.
-//
-// Note: These are hard coded into tblgen.
-//
-class SDNodeProperty;
-def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
-def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node definitions.
-//
-class SDNode<string opcode, SDTypeProfile typeprof,
- list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
- string Opcode = opcode;
- string SDClass = sdclass;
- list<SDNodeProperty> Properties = props;
- SDTypeProfile TypeProfile = typeprof;
-}
-
-def set;
-def node;
-
-def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
-def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
-def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
- [SDNPCommutative, SDNPAssociative]>;
-def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
-def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
- [SDNPCommutative, SDNPAssociative]>;
-def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
-def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
-def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
-def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
-def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
-def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
-def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
-def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
-def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
-def and : SDNode<"ISD::AND" , SDTIntBinOp,
- [SDNPCommutative, SDNPAssociative]>;
-def or : SDNode<"ISD::OR" , SDTIntBinOp,
- [SDNPCommutative, SDNPAssociative]>;
-def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
- [SDNPCommutative, SDNPAssociative]>;
-def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
-def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
-def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
-def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
-def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
-def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
-def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
-def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
-
-def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
-def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node Transformation Functions.
-//
-// This mechanism allows targets to manipulate nodes in the output DAG once a
-// match has been formed. This is typically used to manipulate immediate
-// values.
-//
-class SDNodeXForm<SDNode opc, code xformFunction> {
- SDNode Opcode = opc;
- code XFormFunction = xformFunction;
-}
-
-def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
-
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Fragments.
-//
-// Pattern fragments are reusable chunks of dags that match specific things.
-// They can take arguments and have C++ predicates that control whether they
-// match. They are intended to make the patterns for common instructions more
-// compact and readable.
-//
-
-/// PatFrag - Represents a pattern fragment. This can match something on the
-/// DAG, frame a single node to multiply nested other fragments.
-///
-class PatFrag<dag ops, dag frag, code pred = [{}],
- SDNodeXForm xform = NOOP_SDNodeXForm> {
- dag Operands = ops;
- dag Fragment = frag;
- code Predicate = pred;
- SDNodeXForm OperandTransform = xform;
-}
-
-// PatLeaf's are pattern fragments that have no operands. This is just a helper
-// to define immediates and other common things concisely.
-class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
- : PatFrag<(ops), frag, pred, xform>;
-
-// Leaf fragments.
-
-def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
-def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
-
-def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
-def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
-
-// Other helper fragments.
-
-def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
-def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Support.
-//
-// Patterns are what are actually matched against the target-flavored
-// instruction selection DAG. Instructions defined by the target implicitly
-// define patterns in most cases, but patterns can also be explicitly added when
-// an operation is defined by a sequence of instructions (e.g. loading a large
-// immediate value on RISC targets that do not support immediates as large as
-// their GPRs).
-//
-
-class Pattern<dag patternToMatch, list<dag> resultInstrs> {
- dag PatternToMatch = patternToMatch;
- list<dag> ResultInstrs = resultInstrs;
-}
-
-// Pat - A simple (but common) form of a pattern, which produces a simple result
-// not needing a full list.
-class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
//===----------------------------------------------------------------------===//
// PowerPC specific transformation functions and pattern fragments.
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-22 17:36:17 +0000