diff options
Diffstat (limited to 'lib')
31 files changed, 358 insertions, 348 deletions
diff --git a/lib/Analysis/IPA/CallGraphSCCPass.cpp b/lib/Analysis/IPA/CallGraphSCCPass.cpp index fcf4202826..0640b63e6b 100644 --- a/lib/Analysis/IPA/CallGraphSCCPass.cpp +++ b/lib/Analysis/IPA/CallGraphSCCPass.cpp @@ -82,8 +82,7 @@ bool CGPassManager::runOnModule(Module &M) { I != E; ++I) { // Run all passes on current SCC - for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { - + for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { Pass *P = getContainedPass(Index); AnalysisUsage AnUsage; P->getAnalysisUsage(AnUsage); @@ -95,20 +94,20 @@ bool CGPassManager::runOnModule(Module &M) { StartPassTimer(P); if (CallGraphSCCPass *CGSP = dynamic_cast<CallGraphSCCPass *>(P)) - Changed |= CGSP->runOnSCC(*I); // TODO : What if CG is changed ? + Changed |= CGSP->runOnSCC(*I); // TODO : What if CG is changed ? else { - FPPassManager *FPP = dynamic_cast<FPPassManager *>(P); - assert (FPP && "Invalid CGPassManager member"); - - // Run pass P on all functions current SCC - std::vector<CallGraphNode*> &SCC = *I; - for (unsigned i = 0, e = SCC.size(); i != e; ++i) { - Function *F = SCC[i]->getFunction(); - if (F) { + FPPassManager *FPP = dynamic_cast<FPPassManager *>(P); + assert (FPP && "Invalid CGPassManager member"); + + // Run pass P on all functions current SCC + std::vector<CallGraphNode*> &SCC = *I; + for (unsigned i = 0, e = SCC.size(); i != e; ++i) { + Function *F = SCC[i]->getFunction(); + if (F) { dumpPassInfo(P, EXECUTION_MSG, ON_FUNCTION_MSG, F->getName()); Changed |= FPP->runOnFunction(*F); } - } + } } StopPassTimer(P); @@ -149,7 +148,7 @@ bool CGPassManager::doFinalization(CallGraph &CG) { /// Assign pass manager to manage this pass. void CallGraphSCCPass::assignPassManager(PMStack &PMS, - PassManagerType PreferredType) { + PassManagerType PreferredType) { // Find CGPassManager while (!PMS.empty()) { if (PMS.top()->getPassManagerType() > PMT_CallGraphPassManager) diff --git a/lib/CodeGen/MachOWriter.h b/lib/CodeGen/MachOWriter.h index 061213a8c8..0792ac8a7d 100644 --- a/lib/CodeGen/MachOWriter.h +++ b/lib/CodeGen/MachOWriter.h @@ -254,19 +254,19 @@ namespace llvm { // The following constants are getting pulled in by one of the // system headers, which creates a neat clash with the enum. #if !defined(VM_PROT_NONE) -#define VM_PROT_NONE 0x00 +#define VM_PROT_NONE 0x00 #endif #if !defined(VM_PROT_READ) -#define VM_PROT_READ 0x01 +#define VM_PROT_READ 0x01 #endif #if !defined(VM_PROT_WRITE) -#define VM_PROT_WRITE 0x02 +#define VM_PROT_WRITE 0x02 #endif #if !defined(VM_PROT_EXECUTE) -#define VM_PROT_EXECUTE 0x04 +#define VM_PROT_EXECUTE 0x04 #endif #if !defined(VM_PROT_ALL) -#define VM_PROT_ALL 0x07 +#define VM_PROT_ALL 0x07 #endif // Constants for the vm protection fields diff --git a/lib/CodeGen/README.txt b/lib/CodeGen/README.txt index aa5a54c3ba..8e6b0a5e46 100644 --- a/lib/CodeGen/README.txt +++ b/lib/CodeGen/README.txt @@ -2,29 +2,29 @@ Common register allocation / spilling problem: - mul lr, r4, lr - str lr, [sp, #+52] - ldr lr, [r1, #+32] - sxth r3, r3 - ldr r4, [sp, #+52] - mla r4, r3, lr, r4 + mul lr, r4, lr + str lr, [sp, #+52] + ldr lr, [r1, #+32] + sxth r3, r3 + ldr r4, [sp, #+52] + mla r4, r3, lr, r4 can be: - mul lr, r4, lr + mul lr, r4, lr mov r4, lr - str lr, [sp, #+52] - ldr lr, [r1, #+32] - sxth r3, r3 - mla r4, r3, lr, r4 + str lr, [sp, #+52] + ldr lr, [r1, #+32] + sxth r3, r3 + mla r4, r3, lr, r4 and then "merge" mul and mov: - mul r4, r4, lr - str lr, [sp, #+52] - ldr lr, [r1, #+32] - sxth r3, r3 - mla r4, r3, lr, r4 + mul r4, r4, lr + str lr, [sp, #+52] + ldr lr, [r1, #+32] + sxth r3, r3 + mla r4, r3, lr, r4 It also increase the likelyhood the store may become dead. @@ -70,13 +70,13 @@ Some potential added complexities: bb27 ... ... - %reg1037 = ADDri %reg1039, 1 - %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 + %reg1037 = ADDri %reg1039, 1 + %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 Successors according to CFG: 0x8b03bf0 (#5) bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5): Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4) - %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0> + %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0> Note ADDri is not a two-address instruction. However, its result %reg1037 is an operand of the PHI node in bb76 and its operand %reg1039 is the result of the diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp index e4133cec6e..c6187f1109 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp @@ -288,9 +288,9 @@ private: // Tally iterator /// SlotsAvailable - Returns true if all units are available. - /// + /// bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet, - unsigned &Resource) { + unsigned &Resource) { assert(N && "Must check availability with N != 0"); // Determine end of interval Iter End = Begin + N; @@ -318,23 +318,23 @@ private: Resource = 0; return false; } - - /// RetrySlot - Finds a good candidate slot to retry search. + + /// RetrySlot - Finds a good candidate slot to retry search. Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) { assert(N && "Must check availability with N != 0"); // Determine end of interval Iter End = Begin + N; assert(End <= Tally.end() && "Tally is not large enough for schedule"); - - while (Begin != End--) { - // Clear units in use - ResourceSet &= ~*End; - // If no units left then we should go no further - if (!ResourceSet) return End + 1; - } - // Made it all the way through - return Begin; - } + + while (Begin != End--) { + // Clear units in use + ResourceSet &= ~*End; + // If no units left then we should go no further + if (!ResourceSet) return End + 1; + } + // Made it all the way through + return Begin; + } /// FindAndReserveStages - Return true if the stages can be completed. If /// so mark as busy. @@ -391,13 +391,13 @@ public: // FindAndReserve - Locate an ideal slot for the specified stages and mark // as busy. unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin, - InstrStage *StageEnd) { - // Where to begin - Iter Begin = Tally.begin() + Slot; - // Find a free slot - Iter Where = FindSlots(Begin, StageBegin, StageEnd); - // Distance is slot number - unsigned Final = Where - Tally.begin(); + InstrStage *StageEnd) { + // Where to begin + Iter Begin = Tally.begin() + Slot; + // Find a free slot + Iter Where = FindSlots(Begin, StageBegin, StageEnd); + // Distance is slot number + unsigned Final = Where - Tally.begin(); return Final; } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index d72c6eb01d..7d30062995 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2150,7 +2150,7 @@ static mu magicu64(uint64_t d) /// multiplying by a magic number. See: /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, - std::vector<SDNode*>* Created) const { + std::vector<SDNode*>* Created) const { MVT::ValueType VT = N->getValueType(0); // Check to see if we can do this. @@ -2198,7 +2198,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, /// multiplying by a magic number. See: /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, - std::vector<SDNode*>* Created) const { + std::vector<SDNode*>* Created) const { MVT::ValueType VT = N->getValueType(0); // Check to see if we can do this. diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 6058be114e..2b0450b971 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -53,8 +53,8 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, case ARM::MOVr: case ARM::tMOVr: assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && - MI.getOperand(1).isRegister() && - "Invalid ARM MOV instruction"); + MI.getOperand(1).isRegister() && + "Invalid ARM MOV instruction"); SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index bf6adbd95f..09420071bf 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1372,7 +1372,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { } void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { + MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert((MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET || diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp index 18ff6babf5..0494777aab 100644 --- a/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -53,9 +53,9 @@ namespace { bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); bool PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode); + unsigned OpNo, + unsigned AsmVariant, + const char *ExtraCode); }; } // end of anonymous namespace @@ -278,16 +278,16 @@ bool AlphaAsmPrinter::doFinalization(Module &M) { /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned AsmVariant, + const char *ExtraCode) { printOperand(MI, OpNo); return false; } bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned OpNo, + unsigned AsmVariant, + const char *ExtraCode) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. O << "0("; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 14da957333..2f1eb48068 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -50,7 +50,7 @@ namespace { static int64_t get_ldah16(int64_t x) { int64_t y = x / IMM_MULT; if (x % IMM_MULT > IMM_HIGH) - ++y; + ++y; return y; } @@ -145,7 +145,7 @@ namespace { public: AlphaDAGToDAGISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), - AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) + AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) {} /// getI64Imm - Return a target constant with the specified value, of type @@ -177,7 +177,7 @@ namespace { default: return true; case 'm': // memory Op0 = Op; - AddToISelQueue(Op0); + AddToISelQueue(Op0); break; } @@ -203,7 +203,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { MachineFunction* MF = BB->getParent(); unsigned GP = 0; for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + ee = MF->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R29) { GP = ii->second; break; @@ -219,7 +219,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { MachineFunction* MF = BB->getParent(); unsigned RA = 0; for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + ee = MF->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R26) { RA = ii->second; break; @@ -283,16 +283,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(N1); AddToISelQueue(N2); Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, - SDOperand(0,0)); + SDOperand(0,0)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, - Chain.getValue(1)); + Chain.getValue(1)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, - Chain.getValue(1)); + Chain.getValue(1)); SDNode *CNode = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, - SDOperand(CNode, 1)); + SDOperand(CNode, 1)); return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); } @@ -316,11 +316,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { int64_t val = (int64_t)uval; int32_t val32 = (int32_t)val; if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT && - val >= IMM_LOW + IMM_LOW * IMM_MULT) + val >= IMM_LOW + IMM_LOW * IMM_MULT) break; //(LDAH (LDA)) if ((uval >> 32) == 0 && //empty upper bits - val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT) - // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true + val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT) + // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true break; //(zext (LDAH (LDA))) //Else use the constant pool ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); @@ -328,7 +328,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, - CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); + CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); } case ISD::TargetConstantFP: { ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N); @@ -358,21 +358,21 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { switch(CC) { default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!"); case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: - Opc = Alpha::CMPTEQ; break; + Opc = Alpha::CMPTEQ; break; case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: - Opc = Alpha::CMPTLT; break; + Opc = Alpha::CMPTLT; break; case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: - Opc = Alpha::CMPTLE; break; + Opc = Alpha::CMPTLE; break; case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: - Opc = Alpha::CMPTLT; rev = true; break; + Opc = Alpha::CMPTLT; rev = true; break; case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: - Opc = Alpha::CMPTLE; rev = true; break; + Opc = Alpha::CMPTLE; rev = true; break; case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: - Opc = Alpha::CMPTEQ; inv = true; break; + Opc = Alpha::CMPTEQ; inv = true; break; case ISD::SETO: - Opc = Alpha::CMPTUN; inv = true; break; + Opc = Alpha::CMPTUN; inv = true; break; case ISD::SETUO: - Opc = Alpha::CMPTUN; break; + Opc = Alpha::CMPTUN; break; }; SDOperand tmp1 = N->getOperand(rev?1:0); SDOperand tmp2 = N->getOperand(rev?0:1); @@ -385,12 +385,13 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: - { - SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1, tmp2); - cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, - SDOperand(cmp2, 0), SDOperand(cmp, 0)); - break; - } + { + SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, + tmp1, tmp2); + cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, + SDOperand(cmp2, 0), SDOperand(cmp, 0)); + break; + } default: break; } @@ -403,8 +404,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { case ISD::SELECT: if (MVT::isFloatingPoint(N->getValueType(0)) && - (N->getOperand(0).getOpcode() != ISD::SETCC || - !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) { + (N->getOperand(0).getOpcode() != ISD::SETCC || + !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) { //This should be the condition not covered by the Patterns //FIXME: Don't have SelectCode die, but rather return something testable // so that things like this can be caught in fall though code @@ -427,32 +428,31 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { ConstantSDNode* SC = NULL; ConstantSDNode* MC = NULL; if (N->getOperand(0).getOpcode() == ISD::SRL && - (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) && - (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) - { - uint64_t sval = SC->getValue(); - uint64_t mval = MC->getValue(); - // If the result is a zap, let the autogened stuff handle it. - if (get_zapImm(N->getOperand(0), mval)) - break; - // given mask X, and shift S, we want to see if there is any zap in the - // mask if we play around with the botton S bits - uint64_t dontcare = (~0ULL) >> (64 - sval); - uint64_t mask = mval << sval; - - if (get_zapImm(mask | dontcare)) - mask = mask | dontcare; - - if (get_zapImm(mask)) { - AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Z = - SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, - N->getOperand(0).getOperand(0), - getI64Imm(get_zapImm(mask))), 0); - return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, - getI64Imm(sval)); - } + (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) && + (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) { + uint64_t sval = SC->getValue(); + uint64_t mval = MC->getValue(); + // If the result is a zap, let the autogened stuff handle it. + if (get_zapImm(N->getOperand(0), mval)) + break; + // given mask X, and shift S, we want to see if there is any zap in the + // mask if we play around with the botton S bits + uint64_t dontcare = (~0ULL) >> (64 - sval); + uint64_t mask = mval << sval; + + if (get_zapImm(mask | dontcare)) + mask = mask | dontcare; + + if (get_zapImm(mask)) { + AddToISelQueue(N->getOperand(0).getOperand(0)); + SDOperand Z = + SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, + N->getOperand(0).getOperand(0), + getI64Imm(get_zapImm(mask))), 0); + return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, + getI64Imm(sval)); } + } break; } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 4f636dc8f9..d70fd2aab3 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -172,7 +172,7 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { SDOperand Zero = DAG.getConstant(0, PtrVT); SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); return Lo; } @@ -197,8 +197,8 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { // //#define SP $30 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, - int &VarArgsBase, - int &VarArgsOffset) { + int &VarArgsBase, + int &VarArgsOffset) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); std::vector<SDOperand> ArgValues; @@ -224,17 +224,17 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, abort(); case MVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], - &Alpha::F8RCRegClass); + &Alpha::F8RCRegClass); ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); break; case MVT::f32: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], - &Alpha::F4RCRegClass); + &Alpha::F4RCRegClass); ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); break; case MVT::i64: args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], - &Alpha::GPRCRegClass); + &Alpha::GPRCRegClass); ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64); break; } @@ -286,9 +286,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, - DAG.getNode(AlphaISD::GlobalRetAddr, - MVT::i64), - SDOperand()); + DAG.getNode(AlphaISD::GlobalRetAddr, + MVT::i64), + SDOperand()); switch (Op.getNumOperands()) { default: assert(0 && "Do not know how to return this many arguments!"); @@ -306,7 +306,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { ArgReg = Alpha::F0; } Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); - if(DAG.getMachineFunction().liveout_empty()) + if (DAG.getMachineFunction().liveout_empty()) DAG.getMachineFunction().addLiveOut(ArgReg); break; } @@ -387,8 +387,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, - VarArgsBase, - VarArgsOffset); + VarArgsBase, + VarArgsOffset); case ISD::RET: return LowerRET(Op,DAG); case ISD::JumpTable: return LowerJumpTable(Op, DAG); @@ -420,7 +420,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); return Lo; } @@ -432,18 +432,18 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) { if (GV->hasInternalLinkage()) { SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); return Lo; } else return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); } case ISD::ExternalSymbol: { return DAG.getNode(AlphaISD::RelLit, MVT::i64, - DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op) - ->getSymbol(), MVT::i64), - DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); + DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op) + ->getSymbol(), MVT::i64), + DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); } case ISD::UREM: @@ -452,8 +452,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { if (Op.getOperand(1).getOpcode() == ISD::Constant) { MVT::ValueType VT = Op.Val->getValueType(0); SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? - BuildUDIV(Op.Val, DAG, NULL) : - BuildSDIV(Op.Val, DAG, NULL); + BuildUDIV(Op.Val, DAG, NULL) : + BuildSDIV(Op.Val, DAG, NULL); Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); return Tmp1; @@ -463,10 +463,10 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::UDIV: if (MVT::isInteger(Op.getValueType())) { if (Op.getOperand(1).getOpcode() == ISD::Constant) - return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) - : BuildUDIV(Op.Val, DAG, NULL); + return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) + : BuildUDIV(Op.Val, DAG, NULL); const char* opstr = 0; - switch(Op.getOpcode()) { + switch (Op.getOpcode()) { case ISD::UREM: opstr = "__remqu"; break; case ISD::SREM: opstr = "__remq"; break; case ISD::UDIV: opstr = "__divqu"; break; @@ -591,29 +591,28 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, default: break; // Unknown constriant letter case 'f': return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 , - Alpha::F3 , Alpha::F4 , Alpha |