diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 58 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
2 files changed, 37 insertions, 25 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 9866a26558..bc5f1b69fd 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2350,35 +2350,47 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb), // STRT, STRBT, and STRHT -def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, ldst_so_reg:$addr), - IndexModePost, StFrm, IIC_iStore_ru, - "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strbt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> addr; let Inst{25} = 1; + let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite + let Inst{19-16} = addr; + let Inst{11-5} = offset{11-5}; let Inst{4} = 0; - let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; + let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, addrmode_imm12:$addr), - IndexModePost, StFrm, IIC_iStore_ru, - "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strbt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> addr; let Inst{25} = 0; + let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite - let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; + let Inst{19-16} = addr; + let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } - -def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, ldst_so_reg:$addr), - IndexModePost, StFrm, IIC_iStore_bh_ru, - "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { let Inst{25} = 1; let Inst{21} = 1; // overwrite let Inst{4} = 0; @@ -2386,11 +2398,11 @@ def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, addrmode_imm12:$addr), - IndexModePost, StFrm, IIC_iStore_bh_ru, - "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { let Inst{25} = 0; let Inst{21} = 1; // overwrite let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 85e48c7165..d5994220a0 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -939,8 +939,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STR_POST_REG: case ARM::STRTr: case ARM::STRTi: - case ARM::STRBTr: - case ARM::STRBTi: + case ARM::STRBT_POST_REG: + case ARM::STRBT_POST_IMM: if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; break; default: |