diff options
Diffstat (limited to 'lib')
58 files changed, 397 insertions, 456 deletions
diff --git a/lib/CodeGen/ELFWriter.cpp b/lib/CodeGen/ELFWriter.cpp index eef3d8a65b..474b1c7737 100644 --- a/lib/CodeGen/ELFWriter.cpp +++ b/lib/CodeGen/ELFWriter.cpp @@ -51,6 +51,7 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -65,7 +66,8 @@ char ELFWriter::ID = 0; ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) : MachineFunctionPass(ID), O(o), TM(tm), - OutContext(*new MCContext(*TM.getMCAsmInfo(), new TargetAsmInfo(tm))), + OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(), + new TargetAsmInfo(tm))), TLOF(TM.getTargetLowering()->getObjFileLowering()), is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64), isLittleEndian(TM.getTargetData()->isLittleEndian()), diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index f985af8ba8..f14ee832c3 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -370,7 +370,8 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, // Install a MachineModuleInfo class, which is an immutable pass that holds // all the per-module stuff we're generating, including MCContext. TargetAsmInfo *TAI = new TargetAsmInfo(*this); - MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI); + MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), + *getRegisterInfo(), TAI); PM.add(MMI); OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. diff --git a/lib/CodeGen/MachineModuleInfo.cpp b/lib/CodeGen/MachineModuleInfo.cpp index fadc594efc..2b1c385c1f 100644 --- a/lib/CodeGen/MachineModuleInfo.cpp +++ b/lib/CodeGen/MachineModuleInfo.cpp @@ -254,8 +254,9 @@ void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) { //===----------------------------------------------------------------------===// MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI, + const MCRegisterInfo &MRI, const TargetAsmInfo *TAI) -: ImmutablePass(ID), Context(MAI, TAI), + : ImmutablePass(ID), Context(MAI, MRI, TAI), ObjFileMMI(0), CurCallSite(0), CallsEHReturn(0), CallsUnwindInit(0), DbgInfoAvailable(false), CallsExternalVAFunctionWithFloatingPointArguments(false) { @@ -267,7 +268,7 @@ MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI, } MachineModuleInfo::MachineModuleInfo() -: ImmutablePass(ID), Context(*(MCAsmInfo*)0, NULL) { + : ImmutablePass(ID), Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, NULL) { assert(0 && "This MachineModuleInfo constructor should never be called, MMI " "should always be explicitly constructed by LLVMTargetMachine"); abort(); diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index d5d08e8f69..e5f8ac96d7 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSymbol.h" #include "llvm/ADT/OwningPtr.h" @@ -827,8 +828,8 @@ void MCAsmStreamer::EmitCFIEndProc() { void MCAsmStreamer::EmitRegisterName(int64_t Register) { if (InstPrinter && !MAI.useDwarfRegNumForCFI()) { - const TargetAsmInfo &TAI = getContext().getTargetAsmInfo(); - unsigned LLVMRegister = TAI.getLLVMRegNum(Register, true); + const MCRegisterInfo &MRI = getContext().getRegisterInfo(); + unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true); InstPrinter->printRegName(OS, LLVMRegister); } else { OS << Register; diff --git a/lib/MC/MCContext.cpp b/lib/MC/MCContext.cpp index 8faa72ecb4..21e1489f07 100644 --- a/lib/MC/MCContext.cpp +++ b/lib/MC/MCContext.cpp @@ -9,6 +9,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionCOFF.h" @@ -26,8 +27,9 @@ typedef StringMap<const MCSectionELF*> ELFUniqueMapTy; typedef StringMap<const MCSectionCOFF*> COFFUniqueMapTy; -MCContext::MCContext(const MCAsmInfo &mai, const TargetAsmInfo *tai) : - MAI(mai), TAI(tai), +MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri, + const TargetAsmInfo *tai) : + MAI(mai), MRI(mri), TAI(tai), Allocator(), Symbols(Allocator), UsedNames(Allocator), NextUniqueID(0), CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0), diff --git a/lib/MC/MCDisassembler/Disassembler.cpp b/lib/MC/MCDisassembler/Disassembler.cpp index 5480b4b12b..19d7349bbd 100644 --- a/lib/MC/MCDisassembler/Disassembler.cpp +++ b/lib/MC/MCDisassembler/Disassembler.cpp @@ -41,6 +41,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCRegisterInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); @@ -54,6 +55,9 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(TripleName); assert(MAI && "Unable to create target asm info!"); + const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TripleName); + assert(MRI && "Unable to create target register info!"); + // Package up features to be passed to target/subtarget std::string FeaturesStr; std::string CPU; @@ -70,7 +74,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, assert(tai && "Unable to create target assembler!"); // Set up the MCContext for creating symbols and MCExpr's. - MCContext *Ctx = new MCContext(*MAI, tai); + MCContext *Ctx = new MCContext(*MAI, *MRI, tai); assert(Ctx && "Unable to create MCContext!"); // Set up disassembler. @@ -86,8 +90,8 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType, GetOpInfo, SymbolLookUp, - TheTarget, MAI, TM, tai, Ctx, - DisAsm, IP); + TheTarget, MAI, MRI, TM, tai, + Ctx, DisAsm, IP); assert(DC && "Allocation failure!"); return DC; } diff --git a/lib/MC/MCDisassembler/Disassembler.h b/lib/MC/MCDisassembler/Disassembler.h index f0ec42a017..8740c5c893 100644 --- a/lib/MC/MCDisassembler/Disassembler.h +++ b/lib/MC/MCDisassembler/Disassembler.h @@ -27,6 +27,7 @@ class MCContext; class MCAsmInfo; class MCDisassembler; class MCInstPrinter; +class MCRegisterInfo; class Target; class TargetMachine; @@ -58,6 +59,8 @@ private: const Target *TheTarget; // The assembly information for the target architecture. llvm::OwningPtr<const llvm::MCAsmInfo> MAI; + // The register information for the target architecture. + llvm::OwningPtr<const llvm::MCRegisterInfo> MRI; // The target machine instance. llvm::OwningPtr<llvm::TargetMachine> TM; // The disassembler for the target architecture. @@ -76,6 +79,7 @@ public: LLVMOpInfoCallback getOpInfo, LLVMSymbolLookupCallback symbolLookUp, const Target *theTarget, const MCAsmInfo *mAI, + const MCRegisterInfo *mRI, llvm::TargetMachine *tM, const TargetAsmInfo *tai, llvm::MCContext *ctx, const MCDisassembler *disAsm, MCInstPrinter *iP) : TripleName(tripleName), @@ -83,6 +87,7 @@ public: SymbolLookUp(symbolLookUp), TheTarget(theTarget), Tai(tai) { TM.reset(tM); MAI.reset(mAI); + MRI.reset(mRI); Ctx.reset(ctx); DisAsm.reset(disAsm); IP.reset(iP); diff --git a/lib/MC/MCDisassembler/EDDisassembler.cpp b/lib/MC/MCDisassembler/EDDisassembler.cpp index bdd99afe1a..2e52bec3b9 100644 --- a/lib/MC/MCDisassembler/EDDisassembler.cpp +++ b/lib/MC/MCDisassembler/EDDisassembler.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/AsmLexer.h" @@ -108,6 +109,7 @@ void EDDisassembler::initialize() { InitializeAllTargetInfos(); InitializeAllTargets(); InitializeAllMCAsmInfos(); + InitializeAllMCRegisterInfos(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); InitializeAllDisassemblers(); @@ -186,6 +188,11 @@ EDDisassembler::EDDisassembler(CPUKey &key) : if (!AsmInfo) return; + MRI.reset(Tgt->createMCRegInfo(tripleString)); + + if (!MRI) + return; + Disassembler.reset(Tgt->createMCDisassembler()); if (!Disassembler) @@ -368,7 +375,7 @@ int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands, SourceMgr sourceMgr; sourceMgr.setDiagHandler(diag_handler, static_cast<void*>(this)); sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over - MCContext context(*AsmInfo, NULL); + MCContext context(*AsmInfo, *MRI, NULL); OwningPtr<MCStreamer> streamer(createNullStreamer(context)); OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, diff --git a/lib/MC/MCDisassembler/EDDisassembler.h b/lib/MC/MCDisassembler/EDDisassembler.h index 11d69c151c..217142300b 100644 --- a/lib/MC/MCDisassembler/EDDisassembler.h +++ b/lib/MC/MCDisassembler/EDDisassembler.h @@ -29,22 +29,23 @@ namespace llvm { class AsmLexer; +class AsmParser; class AsmToken; class MCContext; class MCAsmInfo; class MCAsmLexer; -class AsmParser; -class TargetAsmLexer; -class TargetAsmParser; class MCDisassembler; class MCInstPrinter; class MCInst; class MCParsedAsmOperand; +class MCRegisterInfo; class MCStreamer; class MCSubtargetInfo; template <typename T> class SmallVectorImpl; class SourceMgr; class Target; +class TargetAsmLexer; +class TargetAsmParser; class TargetMachine; class TargetRegisterInfo; @@ -140,6 +141,8 @@ struct EDDisassembler { llvm::OwningPtr<llvm::TargetMachine> TargetMachine; /// The assembly information for the target architecture llvm::OwningPtr<const llvm::MCAsmInfo> AsmInfo; + // The register information for the target architecture. + llvm::OwningPtr<const llvm::MCRegisterInfo> MRI; /// The disassembler for the target architecture llvm::OwningPtr<const llvm::MCDisassembler> Disassembler; /// The output string for the instruction printer; must be guarded with diff --git a/lib/MC/MCDwarf.cpp b/lib/MC/MCDwarf.cpp index ad86db13d5..2aab4a3e78 100644 --- a/lib/MC/MCDwarf.cpp +++ b/lib/MC/MCDwarf.cpp @@ -485,11 +485,11 @@ static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol, } static const MachineLocation TranslateMachineLocation( - const TargetAsmInfo &TAI, + const MCRegisterInfo &MRI, const MachineLocation &Loc) { unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ? MachineLocation::VirtualFP : - unsigned(TAI.getDwarfRegNum(Loc.getReg(), true)); + unsigned(MRI.getDwarfRegNum(Loc.getReg(), true)); const MachineLocation &NewLoc = Loc.isReg() ? MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset()); return NewLoc; @@ -771,6 +771,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer, const MCSymbol *lsda, unsigned lsdaEncoding) { MCContext &context = streamer.getContext(); + const MCRegisterInfo &MRI = context.getRegisterInfo(); const TargetAsmInfo &TAI = context.getTargetAsmInfo(); bool verboseAsm = streamer.isVerboseAsm(); @@ -824,7 +825,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer, // Return Address Register if (verboseAsm) streamer.AddComment("CIE Return Address Column"); - streamer.EmitULEB128IntValue(TAI.getDwarfRARegNum(true)); + streamer.EmitULEB128IntValue(MRI.getDwarfRegNum(MRI.getRARegister(), true)); // Augmentation Data Length (optional) @@ -870,9 +871,9 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer, for (int i = 0, n = Moves.size(); i != n; ++i) { MCSymbol *Label = Moves[i].getLabel(); const MachineLocation &Dst = - TranslateMachineLocation(TAI, Moves[i].getDestination()); + TranslateMachineLocation(MRI, Moves[i].getDestination()); const MachineLocation &Src = - TranslateMachineLocation(TAI, Moves[i].getSource()); + TranslateMachineLocation(MRI, Moves[i].getSource()); MCCFIInstruction Inst(Label, Dst, Src); Instructions.push_back(Inst); } diff --git a/lib/MC/MCParser/AsmParser.cpp b/lib/MC/MCParser/AsmParser.cpp index 0c181f3961..055d94c048 100644 --- a/lib/MC/MCParser/AsmParser.cpp +++ b/lib/MC/MCParser/AsmParser.cpp @@ -2416,7 +2416,7 @@ bool GenericAsmParser::ParseRegisterOrRegisterNumber(int64_t &Register, if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc)) return true; - Register = getContext().getTargetAsmInfo().getDwarfRegNum(RegNo, true); + Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true); } else return getParser().ParseAbsoluteExpression(Register); diff --git a/lib/MC/MCParser/COFFAsmParser.cpp b/lib/MC/MCParser/COFFAsmParser.cpp index 66ad384c7d..7fa4d30266 100644 --- a/lib/MC/MCParser/COFFAsmParser.cpp +++ b/lib/MC/MCParser/COFFAsmParser.cpp @@ -12,10 +12,10 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Support/COFF.h" using namespace llvm; @@ -401,12 +401,16 @@ bool COFFAsmParser::ParseAtUnwindOrAtExcept(bool &unwind, bool &except) { bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) { SMLoc startLoc = getLexer().getLoc(); if (getLexer().is(AsmToken::Percent)) { - const TargetAsmInfo &TAI = getContext().getTargetAsmInfo(); + const MCRegisterInfo &MRI = getContext().getRegisterInfo(); SMLoc endLoc; unsigned LLVMRegNo; if (getParser().getTargetParser().ParseRegister(LLVMRegNo,startLoc,endLoc)) return true; +#if 0 + // FIXME: TargetAsmInfo::getCalleeSavedRegs() commits a serious layering + // violation so this validation code is disabled. + // Check that this is a non-volatile register. const unsigned *NVRegs = TAI.getCalleeSavedRegs(); unsigned i; @@ -415,8 +419,9 @@ bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) { break; if (NVRegs[i] == 0) return Error(startLoc, "expected non-volatile register"); +#endif - int SEHRegNo = TAI.getSEHRegNum(LLVMRegNo); + int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo); if (SEHRegNo < 0) return Error(startLoc,"register can't be represented in SEH unwind info"); RegNo = SEHRegNo; diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 14b9a7017c..d41fdb9d2a 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -57,7 +57,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) - : ARMGenRegisterInfo(), TII(tii), STI(sti), + : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), BasePtr(ARM::R6) { } @@ -649,10 +649,6 @@ cannotEliminateFrame(const MachineFunction &MF) const { || needsStackRealignment(MF); } -unsigned ARMBaseRegisterInfo::getRARegister() const { - return ARM::LR; -} - unsigned ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); @@ -672,14 +668,6 @@ unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { return 0; } -int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); -} - -int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { - return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); -} - unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const { switch (Reg) { diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index b4b4059e73..e2d597f3cc 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -164,7 +164,6 @@ public: bool cannotEliminateFrame(const MachineFunction &MF) const; // Debug information queries. - unsigned getRARegister() const; unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getBaseRegister() const { return BasePtr; } @@ -172,9 +171,6 @@ public: unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum, bool isEH) const; - int getLLVMRegNum(unsigned RegNum, bool isEH) const; - bool isLowRegister(unsigned Reg) const; diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index f8fcf2b8af..510f4ab65f 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -117,13 +117,13 @@ extern "C" void LLVMInitializeARMMCInstrInfo() { TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); } -static MCRegisterInfo *createARMMCRegisterInfo() { +static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) { MCRegisterInfo *X = new MCRegisterInfo(); - InitARMMCRegisterInfo(X); + InitARMMCRegisterInfo(X, ARM::LR); return X; } -extern "C" void LLVMInitializeARMMCRegInfo() { +extern "C" void LLVMInitializeARMMCRegisterInfo() { TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); } diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index df8f157266..0f87d14f2d 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -40,8 +40,7 @@ using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) - : AlphaGenRegisterInfo(), - TII(tii) { + : AlphaGenRegisterInfo(Alpha::R26), TII(tii) { } static long getUpper16(long l) { @@ -178,10 +177,6 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } } -unsigned AlphaRegisterInfo::getRARegister() const { - return Alpha::R26; -} - unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |