diff options
Diffstat (limited to 'lib/Target')
41 files changed, 996 insertions, 506 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 874ef43b90..bf50081cc7 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -296,15 +296,13 @@ class RegConstraint<string C> { // ARM specific transformation functions and pattern fragments. // -// imm_neg_XFORM - Return a imm value packed into the format described for -// imm_neg defs below. +// imm_neg_XFORM - Return the negation of an i32 immediate value. def imm_neg_XFORM : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); }]>; -// so_imm_not_XFORM - Return a so_imm value packed into the format described for -// so_imm_not def below. -def so_imm_not_XFORM : SDNodeXForm<imm, [{ +// imm_not_XFORM - Return the complement of a i32 immediate value. +def imm_not_XFORM : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); }]>; @@ -327,7 +325,7 @@ def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; - }], so_imm_not_XFORM> { + }], imm_not_XFORM> { let ParserMatchClass = so_imm_not_asmoperand; } @@ -3269,6 +3267,8 @@ def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), // for part of the negation. def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), (SBCri GPR:$src, so_imm_not:$imm)>; +def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), + (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>; // Note: These are implemented in C++ code, because they have to generate // ADD/SUBrs instructions, which use a complex pattern that a xform function diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 37b280f447..e10f4a865e 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1953,7 +1953,7 @@ def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR), - (t2SBCrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; + (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>; // Select Bytes -- for disassembly only diff --git a/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/lib/Target/ARM/ARMSelectionDAGInfo.cpp index 4c44f69f4d..cb3ac4d1f6 100644 --- a/lib/Target/ARM/ARMSelectionDAGInfo.cpp +++ b/lib/Target/ARM/ARMSelectionDAGInfo.cpp @@ -155,7 +155,8 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, TargetLowering::ArgListEntry Entry; // First argument: data pointer - Type *IntPtrTy = TLI.getDataLayout()->getIntPtrType(*DAG.getContext()); + unsigned AS = DstPtrInfo.getAddrSpace(); + Type *IntPtrTy = TLI.getDataLayout()->getIntPtrType(*DAG.getContext(), AS); Entry.Node = Dst; Entry.Ty = IntPtrTy; Args.push_back(Entry); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 30fa6bc2c7..740548adbc 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -79,7 +79,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget), - STTI(&TLInfo) { + STTI(&TLInfo), VTTI(&TLInfo) { if (!Subtarget.hasARMOps()) report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " "support ARM mode execution!"); @@ -113,7 +113,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget.hasThumb2() ? new ARMFrameLowering(Subtarget) : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)), - STTI(&TLInfo){ + STTI(&TLInfo), VTTI(&TLInfo) { } namespace { diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 227689f897..ddb38687d0 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -47,7 +47,7 @@ static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); O << getShiftOpcStr(ShOpc); - if (ShOpc != ARM_AM::rrx){ + if (ShOpc != ARM_AM::rrx) { O << " "; if (UseMarkup) O << "<imm:"; @@ -67,11 +67,9 @@ ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, } void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - if (UseMarkup) - OS << "<reg:"; - OS << getRegisterName(RegNo); - if (UseMarkup) - OS << ">"; + OS << markup("<reg:") + << getRegisterName(RegNo) + << markup(">"); } void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, @@ -143,12 +141,10 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, return; } - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); - if (UseMarkup) - O << ">"; + O << ", " + << markup("<imm:") + << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) + << markup(">"); printAnnotation(O, Annot); return; } @@ -332,11 +328,9 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, unsigned Reg = Op.getReg(); printRegName(O, Reg); } else if (Op.isImm()) { - if (UseMarkup) - O << "<imm:"; - O << '#' << Op.getImm(); - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << '#' << Op.getImm() + << markup(">"); } else { assert(Op.isExpr() && "unknown operand kind in printOperand"); // If a symbolic branch target was added as a constant expression then print @@ -360,18 +354,9 @@ void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, if (MO1.isExpr()) O << *MO1.getExpr(); else if (MO1.isImm()) { - if (UseMarkup) - O << "<mem:"; - O << "[pc, "; - if (UseMarkup) - O << "<imm:"; - O << "#"; - O << MO1.getImm(); - if (UseMarkup) - O << ">"; - O << "]"; - if (UseMarkup) - O << ">"; + O << markup("<mem:") << "[pc, " + << markup("<imm:") << "#" << MO1.getImm() + << markup(">]>", "]"); } else llvm_unreachable("Unknown LDR label operand?"); @@ -424,25 +409,19 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); if (!MO2.getReg()) { if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0. - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#"; - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())); - O << ARM_AM::getAM2Offset(MO3.getImm()); - if (UseMarkup) - O << ">"; + O << ", " + << markup("<imm:") + << "#" + << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) + << ARM_AM::getAM2Offset(MO3.getImm()) + << markup(">"); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); return; } @@ -452,45 +431,29 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()), ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup); - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); O << ", "; printRegName(O, MO2.getReg()); - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); O << ", "; printRegName(O, MO2.getReg()); - O << ", lsl "; - if (UseMarkup) - O << "<imm:"; - O << "#1"; - if (UseMarkup) - O << ">"; - O << "]"; - if (UseMarkup) - O << ">"; + O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">"); } void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, @@ -520,13 +483,10 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, if (!MO1.getReg()) { unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); - if (UseMarkup) - O << "<imm:"; - O << '#' - << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) - << ImmOffs; - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) + << ImmOffs + << markup(">"); return; } @@ -547,13 +507,9 @@ void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); - O << "], "; - if (UseMarkup) - O << ">"; + O << "], " << markup(">"); if (MO2.getReg()) { O << (char)ARM_AM::getAM3Op(MO3.getImm()); @@ -562,13 +518,11 @@ void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, } unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); - if (UseMarkup) - O << "<imm:"; - O << '#' + O << markup("<imm:") + << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) - << ImmOffs; - if (UseMarkup) - O << ">"; + << ImmOffs + << markup(">"); } void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, @@ -577,18 +531,13 @@ void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); - if (UseMarkup) - O << "<mem:"; - O << '['; + O << markup("<mem:") << '['; printRegName(O, MO1.getReg()); if (MO2.getReg()) { - O << ", "; - O << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())); + O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())); printRegName(O, MO2.getReg()); - O << ']'; - if (UseMarkup) - O << ">"; + O << ']' << markup(">"); return; } @@ -597,18 +546,14 @@ void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); if (ImmOffs || (op == ARM_AM::sub)) { - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#" + O << ", " + << markup("<imm:") + << "#" << ARM_AM::getAddrOpcStr(op) - << ImmOffs; - if (UseMarkup) - O << ">"; + << ImmOffs + << markup(">"); } - O << ']'; - if (UseMarkup) - O << ">"; + O << ']' << markup(">"); } void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, @@ -642,13 +587,9 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, } unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); - if (UseMarkup) - O << "<imm:"; - O << '#' - << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) - << ImmOffs; - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs + << markup(">"); } void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, @@ -656,11 +597,9 @@ void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); unsigned Imm = MO.getImm(); - if (UseMarkup) - O << "<imm:"; - O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff) + << markup(">"); } void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, @@ -677,11 +616,9 @@ void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); unsigned Imm = MO.getImm(); - if (UseMarkup) - O << "<imm:"; - O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2); - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2) + << markup(">"); } @@ -702,26 +639,20 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, return; } - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); if (ImmOffs || Op == ARM_AM::sub) { - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#" + O << ", " + << markup("<imm:") + << "#" << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) - << ImmOffs * 4; - if (UseMarkup) - O << ">"; + << ImmOffs * 4 + << markup(">"); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, @@ -729,29 +660,21 @@ void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); if (MO2.getImm()) { // FIXME: Both darwin as and GNU as violate ARM docs here. O << ", :" << (MO2.getImm() << 3); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, @@ -774,17 +697,9 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, int32_t lsb = CountTrailingZeros_32(v); int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); - if (UseMarkup) - O << "<imm:"; - O << '#' << lsb; - if (UseMarkup) - O << ">"; - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << '#' << width; - if (UseMarkup) - O << ">"; + O << markup("<imm:") << '#' << lsb << markup(">") + << ", " + << markup("<imm:") << '#' << width << markup(">"); } void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, @@ -799,20 +714,16 @@ void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, bool isASR = (ShiftOp & (1 << 5)) != 0; unsigned Amt = ShiftOp & 0x1f; if (isASR) { - O << ", asr "; - if (UseMarkup) - O << "<imm:"; - O << "#" << (Amt == 0 ? 32 : Amt); - if (UseMarkup) - O << ">"; + O << ", asr " + << markup("<imm:") + << "#" << (Amt == 0 ? 32 : Amt) + << markup(">"); } else if (Amt) { - O << ", lsl "; - if (UseMarkup) - O << "<imm:"; - O << "#" << Amt; - if (UseMarkup) - O << ">"; + O << ", lsl " + << markup("<imm:") + << "#" << Amt + << markup(">"); } } @@ -822,12 +733,7 @@ void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, if (Imm == 0) return; assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); - O << ", lsl "; - if (UseMarkup) - O << "<imm:"; - O << "#" << Imm; - if (UseMarkup) - O << ">"; + O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">"); } void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, @@ -837,12 +743,7 @@ void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, if (Imm == 0) Imm = 32; assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); - O << ", asr "; - if (UseMarkup) - O << "<imm:"; - O << "#" << Imm; - if (UseMarkup) - O << ">"; + O << ", asr " << markup("<imm:") << "#" << Imm << markup(">"); } void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, @@ -1024,35 +925,29 @@ void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, int32_t OffImm = (int32_t)MO.getImm(); - if (UseMarkup) - O << "<imm:"; + O << markup("<imm:"); if (OffImm == INT32_MIN) O << "#-0"; else if (OffImm < 0) O << "#-" << -OffImm; else O << "#" << OffImm; - if (UseMarkup) - O << ">"; + O << markup(">"); } void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - if (UseMarkup) - O << "<imm:"; - O << "#" << MI->getOperand(OpNum).getImm() * 4; - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << "#" << MI->getOperand(OpNum).getImm() * 4 + << markup(">"); } void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNum).getImm(); - if (UseMarkup) - O << "<imm:"; - O << "#" << (Imm == 0 ? 32 : Imm); - if (UseMarkup) - O << ">"; + O << markup("<imm:") + << "#" << (Imm == 0 ? 32 : Imm) + << markup(">"); } void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, @@ -1082,17 +977,13 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, return; } - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); if (unsigned RegNum = MO2.getReg()) { O << ", "; printRegName(O, RegNum); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, @@ -1107,21 +998,15 @@ void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, return; } - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); if (unsigned ImmOffs = MO2.getImm()) { - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#" << ImmOffs * Scale; - if (UseMarkup) - O << ">"; + O << ", " + << markup("<imm:") + << "#" << ImmOffs * Scale + << markup(">"); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, @@ -1175,9 +1060,7 @@ void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, return; } - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); int32_t OffImm = (int32_t)MO2.getImm(); @@ -1186,24 +1069,18 @@ void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, if (OffImm == INT32_MIN) OffImm = 0; if (isSub) { - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#-" << -OffImm; - if (UseMarkup) - O << ">"; + O << ", " + << markup("<imm:") + << "#-" << -OffImm + << markup(">"); } else if (OffImm > 0) { - O << ", "; - if (UseMarkup) - O << "<imm:"; - O << "#" << OffImm; - if (UseMarkup) - O << ">"; + O << ", " + << markup("<imm:") + << "#" << OffImm + << markup(">"); } - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, @@ -1212,9 +1089,7 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); int32_t OffImm = (int32_t)MO2.getImm(); @@ -1231,9 +1106,7 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, O << "#" << OffImm; if (OffImm != 0 && UseMarkup) O << ">"; - O << "]"; - if (UseMarkup) - O << ">"; + O << "]" << markup(">"); } void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, @@ -1247,9 +1120,7 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, return; } - if (UseMarkup) - O << "<mem:"; - O << "["; + O << markup("<mem:") << "["; printRegName(O, MO1.getReg()); int32_t OffImm = (int32_t)MO2.getImm(); @@ -1269,9 +1140,7 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, O << "#" << OffImm; if (OffImm != 0 && UseMarkup) O << ">"; - O << "]"; |