diff options
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index e5b300fc77..8f5be6a120 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -17,6 +17,7 @@ #include "ARMFrameLowering.h" #include "ARMMachineFunctionInfo.h" #include "ARMSubtarget.h" +#include "ARMTargetMachine.h" // @LOCALMOD #include "MCTargetDesc/ARMAddressingModes.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" @@ -60,8 +61,10 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, BasePtr(ARM::R6) { } +extern cl::opt<bool> ReserveR9; // @LOCALMOD const uint16_t* ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + if (ReserveR9) return CSR_NaCl_SaveList; // @LOCALMOD bool ghcCall = false; if (MF) { @@ -80,6 +83,7 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const uint32_t* ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { + if (ReserveR9) return CSR_NaCl_RegMask; // @LOCALMOD return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; } @@ -581,6 +585,13 @@ emitLoadConstPool(MachineBasicBlock &MBB, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { + // @LOCALMOD-START + // In the sfi case we do not want to use the load const pseudo instr. + // Sadly, the ARM backend is not very consistent about using this + // pseudo instr. and hence checking this is not sufficient. + // But, it should help detect some regressions early. + assert(!FlagSfiDisableCP && "unexpected call to emitLoadConstPool"); + // @LOCALMOD-END MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); const Constant *C = |