diff options
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 8 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 10 |
2 files changed, 6 insertions, 12 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 3d65dfd31b..367631c60e 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -141,7 +141,7 @@ MachineInstr::SetMachineOperandConst(unsigned i, void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { assert(i < getNumOperands()); // must be explicit op - operands[i].opType = MachineOperand::MO_MachineRegister; + operands[i].opType = MachineOperand::MO_VirtualRegister; operands[i].contents.value = NULL; operands[i].extra.regNum = regNum; } @@ -187,9 +187,6 @@ static void print(const MachineOperand &MO, std::ostream &OS, if (MO.hasAllocatedReg()) OutputReg(OS, MO.getReg(), MRI); break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum(), MRI); - break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); break; @@ -297,9 +294,6 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { OutputValue(OS, MO.getVRegValue()); } break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum()); - break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); break; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 3509b16b6a..2b7b877cb1 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -110,7 +110,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addRegOperand(R->getReg(), MachineOperand::Use); } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { - MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset()); + MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) { MI->addMachineBasicBlockOperand(BB->getBasicBlock()); @@ -143,7 +143,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addConstantPoolIndexOperand(Idx, Offset); } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { - MI->addExternalSymbolOperand(ES->getSymbol(), false); + MI->addExternalSymbolOperand(ES->getSymbol()); } else { assert(Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Flag && @@ -296,7 +296,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, // Add the asm string as an external symbol operand. const char *AsmStr = cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol(); - MI->addExternalSymbolOperand(AsmStr, false); + MI->addExternalSymbolOperand(AsmStr); // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps;) { @@ -311,13 +311,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); - MI->addMachineRegOperand(Reg, MachineOperand::Use); + MI->addRegOperand(Reg, MachineOperand::Use); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); - MI->addMachineRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, MachineOperand::Def); } break; case 3: { // Immediate. |