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-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp47
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp26
5 files changed, 38 insertions, 38 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b7fa207895..e1540ea1d2 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -15,6 +15,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetData.h"
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 53fec718ff..ce0707423e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -18,7 +18,7 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -27,6 +27,13 @@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
+ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
+ const TargetMachine &tm)
+ : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
+ TII = TM.getInstrInfo();
+ MRI = TM.getRegisterInfo();
+ ConstPool = BB->getParent()->getConstantPool();
+}
/// CheckForPhysRegDependency - Check if the dependency between def and use of
/// a specified operand is a physical register dependency. If so, returns the
@@ -341,7 +348,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
const TargetRegisterClass *TRC = 0;
// Figure out the register class to create for the destreg.
if (VRBase)
- TRC = RegMap->getRegClass(VRBase);
+ TRC = RegInfo.getRegClass(VRBase);
else
TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
@@ -351,7 +358,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
VRBase = SrcReg;
} else {
// Create the reg, emit the copy.
- VRBase = RegMap->createVirtualRegister(TRC);
+ VRBase = RegInfo.createVirtualRegister(TRC);
MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
}
@@ -390,7 +397,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
if (VRBase == 0) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
- VRBase = RegMap->createVirtualRegister(RC);
+ VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
}
@@ -437,7 +444,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+ const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
cerr << "Register class of operand and regclass of use don't agree!\n";
#ifndef NDEBUG
@@ -501,7 +508,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
+ assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
}
@@ -565,18 +572,18 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
// Figure out the register class to create for the destreg.
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
- const TargetRegisterClass *TRC = RegMap->getRegClass(VReg);
+ const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
if (VRBase) {
// Grab the destination register
const TargetRegisterClass *DRC = 0;
- DRC = RegMap->getRegClass(VRBase);
+ DRC = RegInfo.getRegClass(VRBase);
assert(SRC == DRC &&
"Source subregister and destination must have the same class");
} else {
// Create the reg
- VRBase = RegMap->createVirtualRegister(SRC);
+ VRBase = RegInfo.createVirtualRegister(SRC);
}
// Add def, source, and subreg index
@@ -626,13 +633,12 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
// Figure out the register class to create for the destreg.
const TargetRegisterClass *TRC = 0;
if (VRBase) {
- TRC = RegMap->getRegClass(VRBase);
+ TRC = RegInfo.getRegClass(VRBase);
} else {
- TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg),
- SubIdx,
+ TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
Node->getValueType(0));
assert(TRC && "Couldn't determine register class for insert_subreg");
- VRBase = RegMap->createVirtualRegister(TRC); // Create the reg
+ VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
}
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -740,7 +746,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
const TargetRegisterClass *TRC = 0;
// Get the target register class
if (MRegisterInfo::isVirtualRegister(InReg))
- TRC = RegMap->getRegClass(InReg);
+ TRC = RegInfo.getRegClass(InReg);
else
TRC =
MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
@@ -847,7 +853,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
} else {
// Copy from physical register.
assert(I->Reg && "Unknown physical register!");
- unsigned VRBase = RegMap->createVirtualRegister(SU->CopyDstRC);
+ unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
assert(isNew && "Node emitted out of order - early");
MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
@@ -864,10 +870,10 @@ void ScheduleDAG::EmitSchedule() {
// block before emitting the code for the block.
MachineFunction &MF = DAG.getMachineFunction();
if (&MF.front() == BB) {
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI)
+ for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
+ E = RegInfo.livein_end(); LI != E; ++LI)
if (LI->second) {
- const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
+ const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
LI->first, RC, RC);
}
@@ -906,11 +912,6 @@ void ScheduleDAG::dumpSchedule() const {
/// Run - perform scheduling.
///
MachineBasicBlock *ScheduleDAG::Run() {
- TII = TM.getInstrInfo();
- MRI = TM.getRegisterInfo();
- RegMap = BB->getParent()->getSSARegMap();
- ConstPool = BB->getParent()->getConstantPool();
-
Schedule();
return BB;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index cf24e46e55..5c7422c97a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -22,7 +22,6 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 6ea7c80687..7ed8bc8a55 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -18,7 +18,6 @@
#define DEBUG_TYPE "pre-RA-sched"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 52d185b5d1..13d3f9720f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -26,14 +26,14 @@
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/ParameterAttributes.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
@@ -166,7 +166,7 @@ namespace llvm {
TargetLowering &TLI;
Function &Fn;
MachineFunction &MF;
- SSARegMap *RegMap;
+ MachineRegisterInfo &RegInfo;
FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
@@ -189,7 +189,7 @@ namespace llvm {
#endif
unsigned MakeReg(MVT::ValueType VT) {
- return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
+ return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
}
/// isExportedInst - Return true if the specified value is an instruction
@@ -244,7 +244,7 @@ static bool isOnlyUsedInEntryBlock(Argument *A) {
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Function &fn, MachineFunction &mf)
- : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
+ : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
// Create a vreg for each argument register that is not dead and is used
// outside of the entry block for the function.
@@ -3348,9 +3348,9 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
- SSARegMap *RegMap = MF.getSSARegMap();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
for (; NumRegs; --NumRegs)
- Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
+ Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
@@ -4363,7 +4363,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
//===----------------------------------------------------------------------===//
unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
- return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
+ return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
@@ -4378,7 +4378,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
AA = &getAnalysis<AliasAnalysis>();
MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
- RegMap = MF.getSSARegMap();
+ RegInfo = &MF.getRegInfo();
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
@@ -4395,9 +4395,9 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
// Add function live-ins to entry block live-in set.
BasicBlock *EntryBB = &Fn.getEntryBlock();
BB = FuncInfo.MBBMap[EntryBB];
- if (!MF.livein_empty())
- for (MachineFunction::livein_iterator I = MF.livein_begin(),
- E = MF.livein_end(); I != E; ++I)
+ if (!RegInfo->livein_empty())
+ for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
+ E = RegInfo->livein_end(); I != E; ++I)
BB->addLiveIn(I->first);
#ifndef NDEBUG
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-24 18:28:18 +0000