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-rw-r--r--include/llvm/CodeGen/MachineInstr.h14
-rw-r--r--include/llvm/CodeGen/MachineInstrBuilder.h14
-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h6
-rw-r--r--include/llvm/Target/TargetInstrInfo.h40
-rw-r--r--include/llvm/Target/TargetMachine.h1
5 files changed, 39 insertions, 36 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 5450e839db..72463f98d8 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -20,7 +20,7 @@
namespace llvm {
-class TargetInstrDescriptor;
+class TargetInstrDesc;
template <typename T> struct ilist_traits;
template <typename T> struct ilist;
@@ -29,7 +29,7 @@ template <typename T> struct ilist;
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr {
- const TargetInstrDescriptor *TID; // Instruction descriptor.
+ const TargetInstrDesc *TID; // Instruction descriptor.
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
@@ -54,14 +54,14 @@ public:
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
- /// TargetInstrDescriptor.
- explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
+ /// TargetInstrDesc.
+ explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
- MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
+ MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
~MachineInstr();
@@ -70,7 +70,7 @@ public:
/// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
- const TargetInstrDescriptor *getDesc() const { return TID; }
+ const TargetInstrDesc &getDesc() const { return *TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
@@ -166,7 +166,7 @@ public:
/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
///
- void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
+ void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 91c4ad9ac1..97d6736ac0 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -22,7 +22,7 @@
namespace llvm {
-class TargetInstrDescriptor;
+class TargetInstrDesc;
class MachineInstrBuilder {
MachineInstr *MI;
@@ -88,14 +88,14 @@ public:
/// BuildMI - Builder interface. Specify how to create the initial instruction
/// itself.
///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
return MachineInstrBuilder(new MachineInstr(TID));
}
/// BuildMI - This version of the builder sets up the first operand as a
/// destination virtual register.
///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID,
unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
}
@@ -106,7 +106,7 @@ inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDescriptor &TID,
+ const TargetInstrDesc &TID,
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
@@ -119,7 +119,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDescriptor &TID) {
+ const TargetInstrDesc &TID) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
return MachineInstrBuilder(MI);
@@ -130,7 +130,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
/// destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDescriptor &TID) {
+ const TargetInstrDesc &TID) {
return BuildMI(*BB, BB->end(), TID);
}
@@ -139,7 +139,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDescriptor &TID,
+ const TargetInstrDesc &TID,
unsigned DestReg) {
return BuildMI(*BB, BB->end(), TID, DestReg);
}
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index a07d0e9482..37c0a9032a 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -31,7 +31,7 @@ namespace llvm {
class SelectionDAG;
class SelectionDAGISel;
class TargetInstrInfo;
- class TargetInstrDescriptor;
+ class TargetInstrDesc;
class TargetMachine;
class TargetRegisterClass;
@@ -335,7 +335,7 @@ namespace llvm {
DenseMap<SDOperand, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
void EmitSchedule();
@@ -353,7 +353,7 @@ namespace llvm {
DenseMap<SDOperand, unsigned> &VRBaseMap);
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
};
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 36ea5c3180..f2d38f4b87 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -82,10 +82,10 @@ public:
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
-/// TargetInstrDescriptor flags - These should be considered private to the
-/// implementation of the TargetInstrDescriptor class. Clients should use the
-/// predicate methods on TargetInstrDescriptor, not use these directly. These
-/// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
+/// TargetInstrDesc flags - These should be considered private to the
+/// implementation of the TargetInstrDesc class. Clients should use the
+/// predicate methods on TargetInstrDesc, not use these directly. These
+/// all correspond to bitfields in the TargetInstrDesc::Flags field.
namespace TID {
enum {
Variadic = 0,
@@ -111,12 +111,12 @@ namespace TID {
};
}
-/// TargetInstrDescriptor - Describe properties that are true of each
+/// TargetInstrDesc - Describe properties that are true of each
/// instruction in the target description file. This captures information about
/// side effects, register use and many other things. There is one instance of
/// this struct for each target instruction class, and the MachineInstr class
/// points to this struct directly to describe itself.
-class TargetInstrDescriptor {
+class TargetInstrDesc {
public:
unsigned short Opcode; // The opcode number.
unsigned short NumOperands; // Num of args (may be more if variable_ops)
@@ -147,6 +147,11 @@ public:
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
+ /// getOpcode - Return the opcode number for this descriptor.
+ unsigned getOpcode() const {
+ return Opcode;
+ }
+
/// getName - Return the name of the record in the .td file for this
/// instruction, for example "ADD8ri".
const char *getName() const {
@@ -421,14 +426,13 @@ public:
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
- const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned NumOpcodes; // number of entries in the desc array
- unsigned numRealOpCodes; // number of non-dummy op codes
+ const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
+ unsigned NumOpcodes; // Number of entries in the desc array
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+ TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant opcodes: All instruction sets have these as their low opcodes.
@@ -445,16 +449,16 @@ public:
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(unsigned Opcode) const {
- assert(Opcode < NumOpcodes);
- return desc[Opcode];
+ const TargetInstrDesc &get(unsigned Opcode) const {
+ assert(Opcode < NumOpcodes && "Invalid opcode!");
+ return Descriptors[Opcode];
}
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
bool isTriviallyReMaterializable(MachineInstr *MI) const {
- return MI->getDesc()->isRematerializable() &&
+ return MI->getDesc().isRematerializable() &&
isReallyTriviallyReMaterializable(MI);
}
@@ -462,9 +466,9 @@ public:
/// effects that are not captured by any operands of the instruction or other
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->hasNoSideEffects()) return false;
- if (!TID->hasConditionalSideEffects()) return true;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.hasNoSideEffects()) return false;
+ if (!TID.hasConditionalSideEffects()) return true;
return !isReallySideEffectFree(MI); // May have side effects
}
protected:
@@ -773,7 +777,7 @@ public:
/// libcodegen, not in libtarget.
class TargetInstrInfoImpl : public TargetInstrInfo {
protected:
- TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+ TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
: TargetInstrInfo(desc, NumOpcodes) {}
public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 726a41536e..36c5d7f8db 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -24,7 +24,6 @@ class TargetAsmInfo;
class TargetData;
class TargetSubtarget;
class TargetInstrInfo;
-class TargetInstrDescriptor;
class TargetJITInfo;
class TargetLowering;
class TargetFrameInfo;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 09:39:19 +0000