diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 8 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 10 | ||||
| -rw-r--r-- | include/llvm/Target/Target.td | 5 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 10 |
4 files changed, 23 insertions, 10 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index ec2d1d7d07..c2f09b7f9c 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -324,6 +324,14 @@ public: return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); } + // This version of getCopyToReg has the register (and its type) as an + // explicit output. + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned Reg, + SDValue N) { + SDVTList VTs = getVTList(MVT::Other, VT); + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); + } // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index ad485103fb..942c169ed9 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -242,14 +242,11 @@ namespace ISD { // remainder result. SDIVREM, UDIVREM, - // CARRY_FALSE - This node is used when folding other nodes, - // like ADDC/SUBC, which indicate the carry result is always false. - CARRY_FALSE, - // Carry-setting nodes for multiple precision addition and subtraction. // These nodes take two operands of the same value type, and produce two // results. The first result is the normal add or sub result, the second - // result is the carry flag result. + // result is the carry flag result (type i1 or whatever it got expanded to + // for the target, value 0 or 1). ADDC, SUBC, // Carry-using nodes for multiple precision addition and subtraction. These @@ -258,7 +255,8 @@ namespace ISD { // produce two results; the normal result of the add or sub, and the output // carry flag. These nodes both read and write a carry flag to allow them // to them to be chained together for add and sub of arbitrarily large - // values. + // values. The carry flag (input and output) has type i1 or whatever it + // got expanded to for the target, and has value 0 or 1. ADDE, SUBE, // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 3f1cdd27ca..4af108925f 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -326,6 +326,11 @@ class InstrInfo { // Sparc manual specifies its instructions in the format [31..0] (big), while // PowerPC specifies them using the format [0..31] (little). bit isLittleEndianEncoding = 0; + + // Targets that can support the HasI1 argument on ADDC and ADDE, rather than + // Flag, have this bit set. This is transitional and should go away when all + // targets have been switched over. + bit supportsHasI1 = 0; } // Standard Instructions. diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 2cd29676db..2586e65d39 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -216,6 +216,8 @@ def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result //===----------------------------------------------------------------------===// // Selection DAG Node definitions. @@ -289,13 +291,13 @@ def or : SDNode<"ISD::OR" , SDTIntBinOp, def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, - [SDNPCommutative, SDNPOutFlag]>; + [SDNPCommutative, SDNPOutI1]>; def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, - [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, - [SDNPOutFlag]>; + [SDNPOutI1]>; def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, - [SDNPOutFlag, SDNPInFlag]>; + [SDNPInI1, SDNPOutI1]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; |