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-rw-r--r--include/llvm/CodeGen/AsmPrinter.h7
-rw-r--r--include/llvm/CodeGen/DwarfWriter.h3
-rw-r--r--include/llvm/CodeGen/LinkAllCodegenComponents.h11
-rw-r--r--include/llvm/CodeGen/SchedulerRegistry.h14
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h8
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h5
6 files changed, 27 insertions, 21 deletions
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index 3f61d74e13..727fd61963 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -16,9 +16,10 @@
#ifndef LLVM_CODEGEN_ASMPRINTER_H
#define LLVM_CODEGEN_ASMPRINTER_H
+#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DataTypes.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/Target/TargetMachine.h"
#include <set>
namespace llvm {
@@ -66,7 +67,7 @@ namespace llvm {
std::set<const GlobalValue*> ExtWeakSymbols;
/// OptLevel - Generating code at a specific optimization level.
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
public:
/// Output stream on which we're printing assembly code.
///
@@ -111,7 +112,7 @@ namespace llvm {
protected:
explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V);
+ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
public:
virtual ~AsmPrinter();
diff --git a/include/llvm/CodeGen/DwarfWriter.h b/include/llvm/CodeGen/DwarfWriter.h
index 5641407001..e4e485039e 100644
--- a/include/llvm/CodeGen/DwarfWriter.h
+++ b/include/llvm/CodeGen/DwarfWriter.h
@@ -21,6 +21,7 @@
#define LLVM_CODEGEN_DWARFWRITER_H
#include "llvm/Pass.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -81,7 +82,7 @@ public:
void EndFunction(MachineFunction *MF);
/// ValidDebugInfo - Return true if V represents valid debug info value.
- bool ValidDebugInfo(Value *V, unsigned OptLevel);
+ bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
/// RecordSourceLine - Register a source line with debug info. Returns a
/// unique label ID used to generate a label and provide correspondence to
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 84d9819c2d..a231f49d81 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/GCs.h"
+#include "llvm/Target/TargetMachine.h"
namespace {
struct ForceCodegenLinking {
@@ -42,11 +43,11 @@ namespace {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
- (void) llvm::createBURRListDAGScheduler(NULL, 3);
- (void) llvm::createTDRRListDAGScheduler(NULL, 3);
- (void) llvm::createTDListDAGScheduler(NULL, 3);
- (void) llvm::createFastDAGScheduler(NULL, 3);
- (void) llvm::createDefaultScheduler(NULL, 3);
+ (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
}
} ForceCodegenLinking; // Force link by creating a global definition.
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index e02dc7a392..1cf64a09a7 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -16,6 +16,7 @@
#define LLVM_CODEGENSCHEDULERREGISTRY_H
#include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -32,7 +33,8 @@ class MachineBasicBlock;
class RegisterScheduler : public MachinePassRegistryNode {
public:
- typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+ typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
+ CodeGenOpt::Level);
static MachinePassRegistry Registry;
@@ -64,27 +66,27 @@ public:
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
} // end namespace llvm
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 90603769d9..74aa8ff820 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -20,7 +20,7 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <vector>
#include <map>
@@ -30,7 +30,6 @@ namespace llvm {
class AliasAnalysis;
class TargetLowering;
-class TargetMachine;
class MachineModuleInfo;
class DwarfWriter;
class MachineFunction;
@@ -202,7 +201,8 @@ public:
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
- void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+ void Combine(CombineLevel Level, AliasAnalysis &AA,
+ CodeGenOpt::Level OptLevel);
/// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
/// only uses types natively supported by the target. Returns "true" if it
@@ -218,7 +218,7 @@ public:
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
- void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+ void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
/// RemoveDeadNodes - This method deletes all unreachable nodes in the
/// SelectionDAG.
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index d8802c7d9d..05a047563a 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -51,10 +51,11 @@ public:
MachineBasicBlock *BB;
AliasAnalysis *AA;
GCFunctionInfo *GFI;
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
static char ID;
- explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+ explicit SelectionDAGISel(TargetMachine &tm,
+ CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-03 23:09:21 +0000