diff options
Diffstat (limited to 'include/llvm/CodeGen')
| -rw-r--r-- | include/llvm/CodeGen/LinkAllCodegenComponents.h | 8 | ||||
| -rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 12 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SchedulerRegistry.h | 2 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 5 |
4 files changed, 16 insertions, 11 deletions
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h index ac58035593..39df7337ba 100644 --- a/include/llvm/CodeGen/LinkAllCodegenComponents.h +++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h @@ -39,10 +39,10 @@ namespace { (void) llvm::createOcamlCollector(); (void) llvm::createShadowStackCollector(); - (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL); - (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL); - (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL); - (void) llvm::createDefaultScheduler(NULL, NULL, NULL); + (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, false); + (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, false); + (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, false); + (void) llvm::createDefaultScheduler(NULL, NULL, NULL, false); } } ForceCodegenLinking; // Force link by creating a global definition. diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 4849f914ca..ed7801fbfc 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -396,25 +396,29 @@ namespace llvm { /// reduction list scheduler. ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + MachineBasicBlock *BB, + bool Fast); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + MachineBasicBlock *BB, + bool Fast); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + MachineBasicBlock *BB, + bool Fast); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + MachineBasicBlock *BB, + bool Fast); class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { SUnit *Node; diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index 4c34121d54..db70dee6c5 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -35,7 +35,7 @@ class RegisterScheduler : public MachinePassRegistryNode { public: typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*, - MachineBasicBlock*); + MachineBasicBlock*, bool); static MachinePassRegistry Registry; diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 7925a00792..3ebe515b38 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -44,10 +44,11 @@ public: std::vector<SDNode*> TopOrder; unsigned DAGSize; CollectorMetadata *GCI; + bool FastISel; static char ID; - explicit SelectionDAGISel(TargetLowering &tli) : - FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {} + explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : + FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0), FastISel(fast) {} TargetLowering &getTargetLowering() { return TLI; } |