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Diffstat (limited to 'include/llvm/CodeGen/SelectionDAGNodes.h')
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index f2ff91abf3..5cfc1661a0 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -332,6 +332,14 @@ namespace ISD { // (op #2) as a CondCodeSDNode. SETCC, + // Vector SetCC operator - This evaluates to a vector of integer elements + // with the high bit in each element set to true if the comparison is true + // and false if the comparison is false. All other bits in each element + // are undefined. The operands to this are the left and right operands + // to compare (ops #0, and #1) and the condition code to compare them with + // (op #2) as a CondCodeSDNode. + VSETCC, + // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded // integer shift operations, just like ADD/SUB_PARTS. The operation // ordering is: |