aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/llvm/Support/MathExtras.h10
-rw-r--r--lib/Target/Blackfin/BlackfinInstrInfo.td22
-rw-r--r--lib/Target/Blackfin/BlackfinRegisterInfo.cpp14
-rw-r--r--lib/Target/Blackfin/BlackfinRegisterInfo.h10
4 files changed, 28 insertions, 28 deletions
diff --git a/include/llvm/Support/MathExtras.h b/include/llvm/Support/MathExtras.h
index a143d1975d..15a67e4029 100644
--- a/include/llvm/Support/MathExtras.h
+++ b/include/llvm/Support/MathExtras.h
@@ -52,6 +52,16 @@ inline bool isUInt32(int64_t Value) {
return static_cast<uint32_t>(Value) == Value;
}
+template<unsigned N>
+inline bool isInt(int64_t x) {
+ return -(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1));
+}
+
+template<unsigned N>
+inline bool isUint(uint64_t x) {
+ return x < (UINT64_C(1)<<N);
+}
+
/// isMask_32 - This function returns true if the argument is a sequence of ones
/// starting at the least significant bit with the remainder zero (32 bit
/// version). Ex. isMask_32(0x0000FFFFU) == true.
diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.td b/lib/Target/Blackfin/BlackfinInstrInfo.td
index b0a2cc13c4..934b18864c 100644
--- a/lib/Target/Blackfin/BlackfinInstrInfo.td
+++ b/lib/Target/Blackfin/BlackfinInstrInfo.td
@@ -63,24 +63,24 @@ def HI16 : SDNodeXForm<imm, [{
// Immediates
//===----------------------------------------------------------------------===//
-def imm3 : PatLeaf<(imm), [{return isImm<3>(N->getSExtValue());}]>;
-def uimm3 : PatLeaf<(imm), [{return isUimm<3>(N->getZExtValue());}]>;
-def uimm4 : PatLeaf<(imm), [{return isUimm<4>(N->getZExtValue());}]>;
-def uimm5 : PatLeaf<(imm), [{return isUimm<5>(N->getZExtValue());}]>;
+def imm3 : PatLeaf<(imm), [{return isInt<3>(N->getSExtValue());}]>;
+def uimm3 : PatLeaf<(imm), [{return isUint<3>(N->getZExtValue());}]>;
+def uimm4 : PatLeaf<(imm), [{return isUint<4>(N->getZExtValue());}]>;
+def uimm5 : PatLeaf<(imm), [{return isUint<5>(N->getZExtValue());}]>;
def uimm5m2 : PatLeaf<(imm), [{
uint64_t value = N->getZExtValue();
- return value % 2 == 0 && isUimm<5>(value);
+ return value % 2 == 0 && isUint<5>(value);
}]>;
def uimm6m4 : PatLeaf<(imm), [{
uint64_t value = N->getZExtValue();
- return value % 4 == 0 && isUimm<6>(value);
+ return value % 4 == 0 && isUint<6>(value);
}]>;
-def imm7 : PatLeaf<(imm), [{return isImm<7>(N->getSExtValue());}]>;
-def imm16 : PatLeaf<(imm), [{return isImm<16>(N->getSExtValue());}]>;
-def uimm16 : PatLeaf<(imm), [{return isUimm<16>(N->getZExtValue());}]>;
+def imm7 : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
+def imm16 : PatLeaf<(imm), [{return isInt<16>(N->getSExtValue());}]>;
+def uimm16 : PatLeaf<(imm), [{return isUint<16>(N->getZExtValue());}]>;
def ximm16 : PatLeaf<(imm), [{
int64_t value = N->getSExtValue();
@@ -89,12 +89,12 @@ def ximm16 : PatLeaf<(imm), [{
def imm17m2 : PatLeaf<(imm), [{
int64_t value = N->getSExtValue();
- return value % 2 == 0 && isImm<17>(value);
+ return value % 2 == 0 && isInt<17>(value);
}]>;
def imm18m4 : PatLeaf<(imm), [{
int64_t value = N->getSExtValue();
- return value % 4 == 0 && isImm<18>(value);
+ return value % 4 == 0 && isInt<18>(value);
}]>;
// 32-bit bitmask transformed to a bit number
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
index 1b3dfece7a..7fcfd12696 100644
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
@@ -128,7 +128,7 @@ void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
int delta) const {
if (!delta)
return;
- if (isImm<7>(delta)) {
+ if (isInt<7>(delta)) {
BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
.addReg(Reg) // No kill on two-addr operand
.addImm(delta);
@@ -159,17 +159,17 @@ void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
DebugLoc DL,
unsigned Reg,
int value) const {
- if (isImm<7>(value)) {
+ if (isInt<7>(value)) {
BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
return;
}
- if (isUimm<16>(value)) {
+ if (isUint<16>(value)) {
BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
return;
}
- if (isImm<16>(value)) {
+ if (isInt<16>(value)) {
BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
return;
}
@@ -254,20 +254,20 @@ void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(FIPos==1 && "Bad frame index operand");
MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
MI.getOperand(FIPos+1).setImm(Offset);
- if (isUimm<6>(Offset)) {
+ if (isUint<6>(Offset)) {
MI.setDesc(TII.get(isStore
? BF::STORE32p_uimm6m4
: BF::LOAD32p_uimm6m4));
return;
}
- if (BaseReg == BF::FP && isUimm<7>(-Offset)) {
+ if (BaseReg == BF::FP && isUint<7>(-Offset)) {
MI.setDesc(TII.get(isStore
? BF::STORE32fp_nimm7m4
: BF::LOAD32fp_nimm7m4));
MI.getOperand(FIPos+1).setImm(-Offset);
return;
}
- if (isImm<18>(Offset)) {
+ if (isInt<18>(Offset)) {
MI.setDesc(TII.get(isStore
? BF::STORE32p_imm18m4
: BF::LOAD32p_imm18m4));
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.h b/lib/Target/Blackfin/BlackfinRegisterInfo.h
index 83abc2ef11..57aea5d3dc 100644
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.h
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.h
@@ -24,16 +24,6 @@ namespace llvm {
class TargetInstrInfo;
class Type;
- template<unsigned N>
- static inline bool isImm(int x) {
- return x >= -(1<<(N-1)) && x < (1<<(N-1));
- }
-
- template<unsigned N>
- static inline bool isUimm(unsigned x) {
- return x < (1<<N);
- }
-
// Subregister indices, keep in sync with BlackfinRegisterInfo.td
enum BfinSubregIdx {
bfin_subreg_lo16 = 1,
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-03 01:31:16 +0000