diff options
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index a0992c1c46..ddf445d7a9 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -44,7 +44,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, LoopRegs(MLI, MDT), FirstDbgValue(0) { assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); DbgValues.clear(); - assert(!(IsPostRA && MF.getRegInfo().getNumVirtRegs()) && + assert(!(IsPostRA && MRI.getNumVirtRegs()) && "Virtual registers must be removed prior to PostRA scheduling"); } @@ -361,6 +361,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { const MachineInstr *MI = SU->getInstr(); unsigned Reg = MI->getOperand(OperIdx).getReg(); + // SSA defs do not have output/anti dependencies. + if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) + return; + // Add output dependence to the next nearest def of this vreg. // // Unless this definition is dead, the output dependence should be |