diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 2 |
2 files changed, 1 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 7186fe51af..0ec11ac98f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -207,10 +207,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, X86::FR32RegisterClass); addRegisterClass(MVT::f64, X86::FR64RegisterClass); - // SSE has no load+extend ops - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); - // Use ANDPD to simulate FABS. setOperationAction(ISD::FABS , MVT::f64, Custom); setOperationAction(ISD::FABS , MVT::f32, Custom); diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 6b799945b9..3c1db67146 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -526,7 +526,7 @@ def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), Requires<[HasSSE2]>; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, + [(set FR64:$dst, (extload addr:$src, f32))]>, XS, Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). |