diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 13 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-printf.txt | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-tests.txt | 3 | ||||
| -rw-r--r-- | utils/TableGen/ARMDecoderEmitter.cpp | 5 |
4 files changed, 24 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 9c88c10315..eab38272ec 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -721,6 +721,19 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, let Inst{7-0} = addr; } +// FIXME: Remove this entry when the above ldr.n workaround is fixed. +// For disassembly use only. +def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, + "ldr", "\t$Rt, $addr", + [/* disassembly only */]>, + T1Encoding<{0,1,0,0,1,?}> { + // A6.2 & A8.6.59 + bits<3> Rt; + bits<8> addr; + let Inst{10-8} = Rt; + let Inst{7-0} = addr; +} + // A8.6.194 & A8.6.192 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, t_addrmode_is4, AddrModeT1_4, diff --git a/test/MC/Disassembler/ARM/thumb-printf.txt b/test/MC/Disassembler/ARM/thumb-printf.txt index 09f54abf82..6c2c500630 100644 --- a/test/MC/Disassembler/ARM/thumb-printf.txt +++ b/test/MC/Disassembler/ARM/thumb-printf.txt @@ -7,17 +7,17 @@ # CHECK-NEXT: add r3, sp, #20 # CHECK-NEXT: ldr r5, [r3], #4 # CHECK-NEXT: str r3, [sp] -# CHECK-NEXT: ldr.n r3, #52 +# CHECK-NEXT: ldr r3, #52 # CHECK-NEXT: add r3, pc # CHECK-NEXT: ldr r0, [r3] # CHECK-NEXT: ldr r4, [r0] -# CHECK-NEXT: ldr.n r0, #48 +# CHECK-NEXT: ldr r0, #48 # CHECK-NEXT: add r0, pc # CHECK-NEXT: ldr r0, [r0] # CHECK-NEXT: ldr r0, [r0] # CHECK-NEXT: blx #191548 # CHECK-NEXT: cbnz r0, #6 -# CHECK-NEXT: ldr.n r1, #40 +# CHECK-NEXT: ldr r1, #40 # CHECK-NEXT: add r1, pc # CHECK-NEXT: ldr r1, [r1] # CHECK-NEXT: b #0 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 39030a8b37..2cbb33cec7 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -30,6 +30,9 @@ # CHECK: ldmia r0!, {r1} 0x02 0xc8 +# CHECK: ldr r5, #432 +0x6c 0x4d + # CHECK: str r0, [r3] 0x18 0x60 diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index ed44f821a2..62bd1c65e4 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1652,6 +1652,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") return false; + // FIXME: Use ldr.n to work around a Darwin assembler bug. + // Introduce a workaround with tLDRpciDIS opcode. + if (Name == "tLDRpci") + return false; + // Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST. if (Name == "t2LDRDpci") return false; |