diff options
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/trap.ll | 11 |
3 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 5b898af6d6..a3ea907e96 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -404,6 +404,8 @@ MipsTargetLowering(MipsTargetMachine &TM) // @LOCALMOD-END + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setTargetDAGCombine(ISD::SDIVREM); setTargetDAGCombine(ISD::UDIVREM); setTargetDAGCombine(ISD::SELECT); diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 849544cf22..e3180f8f39 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -803,6 +803,11 @@ class SCBase<string opstr, RegisterOperand RO, Operand Mem> : class MFC3OP<dag outs, dag ins, string asmstr> : InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; +let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in +def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> { + let Inst = 0x0000000d; +} + //===----------------------------------------------------------------------===// // Pseudo instructions //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/Mips/trap.ll b/test/CodeGen/Mips/trap.ll new file mode 100644 index 0000000000..beb4b89463 --- /dev/null +++ b/test/CodeGen/Mips/trap.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s + +declare void @llvm.trap() + +define void @f1() { +entry: + call void @llvm.trap() + unreachable + +; CHECK: break +} |