diff options
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/X86/X86NaClRewritePass.cpp | 20 |
2 files changed, 31 insertions, 3 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 0b213e9a90..318f2398e5 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -578,6 +578,20 @@ bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { // If all else fails, try to materialize the value in a register. if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { + // @LOCALMOD-START + if (Subtarget->isTargetNaCl()) { + // We can materialize into a memory address only if + // no registers have been defined (and hence, we + // aren't modifying an existing memory reference). + if ((AM.Base.Reg == 0) && (AM.IndexReg == 0)) { + // Put into index register so that the NaCl rewrite pass will + // convert this to a 64-bit address. + AM.IndexReg = getRegForValue(V); + return AM.IndexReg != 0; + } + return false; + } + // @LOCALMOD-END if (AM.Base.Reg == 0) { AM.Base.Reg = getRegForValue(V); return AM.Base.Reg != 0; diff --git a/lib/Target/X86/X86NaClRewritePass.cpp b/lib/Target/X86/X86NaClRewritePass.cpp index d78de24924..86bb45584e 100644 --- a/lib/Target/X86/X86NaClRewritePass.cpp +++ b/lib/Target/X86/X86NaClRewritePass.cpp @@ -536,9 +536,23 @@ bool X86NaClRewritePass::ApplyMemorySFI(MachineBasicBlock &MBB, assert(Scale.getImm() == 1); AddrReg = 0; } else { - assert(!BaseReg.getReg() && "Unexpected relative register pair"); - BaseReg.setReg(UseZeroBasedSandbox ? 0 : X86::R15); - AddrReg = IndexReg.getReg(); + if (!BaseReg.getReg()) { + // No base, fill in relative. + BaseReg.setReg(UseZeroBasedSandbox ? 0 : X86::R15); + AddrReg = IndexReg.getReg(); + } else if (!UseZeroBasedSandbox) { + // Switch base and index registers if index register is undefined. + // That is do conversions like "mov d(%r,0,0) -> mov d(%r15, %r, 1)". + assert (!IndexReg.getReg() + && "Unexpected index and base register"); + IndexReg.setReg(BaseReg.getReg()); + Scale.setImm(1); + BaseReg.setReg(X86::R15); + AddrReg = IndexReg.getReg(); + } else { + llvm_unreachable( + "Unexpected index and base register"); + } } if (AddrReg) { |