diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 14 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 28 |
2 files changed, 38 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index c7ef149e75..89a0e7e02d 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -451,6 +451,7 @@ class AI3ldh<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AXI3ldh<dag oops, dag iops, Format f, string asm, list<dag> pattern> @@ -475,6 +476,7 @@ class AI3ldsh<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AXI3ldsh<dag oops, dag iops, Format f, string asm, list<dag> pattern> @@ -499,6 +501,7 @@ class AI3ldsb<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AXI3ldsb<dag oops, dag iops, Format f, string asm, list<dag> pattern> @@ -523,6 +526,7 @@ class AI3ldd<dag oops, dag iops, Format f, string opc, let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } // stores @@ -537,6 +541,7 @@ class AI3sth<dag oops, dag iops, Format f, string opc, let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AXI3sth<dag oops, dag iops, Format f, string asm, list<dag> pattern> @@ -561,6 +566,7 @@ class AI3std<dag oops, dag iops, Format f, string opc, let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } // Pre-indexed loads @@ -575,6 +581,7 @@ class AI3ldhpr<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AI3ldshpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> @@ -587,6 +594,7 @@ class AI3ldshpr<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } class AI3ldsbpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> @@ -599,6 +607,7 @@ class AI3ldsbpr<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } // Pre-indexed stores @@ -613,6 +622,7 @@ class AI3sthpr<dag oops, dag iops, Format f, string opc, let Inst{20} = 0; // L bit let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit + let Inst{27-25} = 0b000; } // Post-indexed loads @@ -627,6 +637,7 @@ class AI3ldhpo<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit + let Inst{27-25} = 0b000; } class AI3ldshpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> @@ -639,6 +650,7 @@ class AI3ldshpo<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit + let Inst{27-25} = 0b000; } class AI3ldsbpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> @@ -651,6 +663,7 @@ class AI3ldsbpo<dag oops, dag iops, Format f, string opc, let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit + let Inst{27-25} = 0b000; } // Post-indexed stores @@ -665,6 +678,7 @@ class AI3sthpo<dag oops, dag iops, Format f, string opc, let Inst{20} = 0; // L bit let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit + let Inst{27-25} = 0b000; } diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 3fd63f01b3..2b7192321d 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -91,24 +91,44 @@ let mayLoad = 1 in { def VLDMD : NI<(outs), (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), "vldm${addr:submode} ${addr:base}, $dst1", - []>; + []> { + let Inst{27-25} = 0b110; + let Inst{20} = 1; + let Inst{11-9} = 0b101; +} def VLDMS : NI<(outs), (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), "vldm${addr:submode} ${addr:base}, $dst1", - []>; + []> { + let Inst{27-25} = 0b110; + let Inst{20} = 1; + let Inst{11-9} = 0b101; +} } */ // Use vldmia to load a Q register as a D register pair. def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr), "vldmia $addr, ${dst:dregpair}", - [(set QPR:$dst, (v2f64 (load GPR:$addr)))]>; + [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> { + let Inst{27-25} = 0b110; + let Inst{24} = 0; // P bit + let Inst{23} = 1; // U bit + let Inst{20} = 1; + let Inst{11-9} = 0b101; +} // Use vstmia to store a Q register as a D register pair. def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr), "vstmia $addr, ${src:dregpair}", - [(store (v2f64 QPR:$src), GPR:$addr)]>; + [(store (v2f64 QPR:$src), GPR:$addr)]> { + let Inst{27-25} = 0b110; + let Inst{24} = 0; // P bit + let Inst{23} = 1; // U bit + let Inst{20} = 0; + let Inst{11-9} = 0b101; +} // VLD1 : Vector Load (multiple single elements) |