diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMNaClRewritePass.cpp | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 118c9ea5dd..ab8b2356a3 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1596,7 +1596,7 @@ PseudoInst<(outs GPR:$dst), (ins GPR:$a, pred:$p), NoItinerary, []>; let Defs = [CPSR] in def SFI_GUARD_LOADSTORE_TST : -PseudoInst<(outs GPR:$dst), (ins GPR:$a), NoItinerary, []>; +PseudoInst<(outs), (ins GPR:$a), NoItinerary, []>; // Like SFI_GUARD_LOADSTORE, but reserved for loads into SP. def SFI_GUARD_SP_LOAD : diff --git a/lib/Target/ARM/ARMNaClRewritePass.cpp b/lib/Target/ARM/ARMNaClRewritePass.cpp index 89ce479a90..341d52ea1d 100644 --- a/lib/Target/ARM/ARMNaClRewritePass.cpp +++ b/lib/Target/ARM/ARMNaClRewritePass.cpp @@ -547,8 +547,7 @@ void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB, // Instruction can be predicated -- use the new sandbox. BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SFI_GUARD_LOADSTORE_TST)) - .addReg(Addr, RegState::Define) // Address definition (as dst) - .addReg(Addr, RegState::Kill); // Address read (as src) + .addReg(Addr); // Address read (as src) } else { unsigned Opcode; if (IsLoad && (MI.getOperand(0).getReg() == ARM::SP)) { |