diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index d7449fee2b..01aefb54cc 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -285,8 +285,8 @@ def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs), "add $dst, pc, $rhs * 4", []>; def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs), "add $dst, $sp, $rhs * 4", []>; -def tADDspi : TI<(ops GPR:$sp, i32imm:$rhs), - "add $sp, $rhs * 4", []>; +def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), + "add $dst, $rhs * 4", []>; def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), @@ -413,8 +413,8 @@ def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), "sub $dst, $lhs, $rhs", [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>; -def tSUBspi : TI<(ops GPR:$sp, i32imm:$rhs), - "sub $sp, $rhs * 4", []>; +def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs), + "sub $dst, $rhs * 4", []>; def tSXTB : TI<(ops GPR:$dst, GPR:$src), "sxtb $dst, $src", diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 68eb616d7f..912d17adc1 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -378,7 +378,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, Bytes -= ThisVal; // Build the new tADD / tSUB. if (isTwoAddr) - BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal); else { BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal); BaseReg = DestReg; |