diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 11 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 2 | ||||
| -rw-r--r-- | test/MC/ARM/neon-mul-encoding.s | 8 |
3 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 5bc67660db..58fc019032 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5708,6 +5708,17 @@ def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm", def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm", (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>; +// Two-operand variants for VQDMULH +def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm", + (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm", + (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; + +def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm", + (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm", + (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; + // 'gas' compatibility aliases for quad-word instructions. Strictly speaking, // these should restrict to just the Q register variants, but the register // classes are enough to match correctly regardless, so we keep it simple diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 674b38ebfb..5d4355613d 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -1192,6 +1192,8 @@ def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; def : VFP2MnemonicAlias<"fsts", "vstr">; def : VFP2MnemonicAlias<"fstd", "vstr">; +def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; +def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", diff --git a/test/MC/ARM/neon-mul-encoding.s b/test/MC/ARM/neon-mul-encoding.s index 5b9831e969..d6bc1f3291 100644 --- a/test/MC/ARM/neon-mul-encoding.s +++ b/test/MC/ARM/neon-mul-encoding.s @@ -51,12 +51,20 @@ vqdmulh.s32 d16, d16, d17 vqdmulh.s16 q8, q8, q9 vqdmulh.s32 q8, q8, q9 + vqdmulh.s16 d16, d17 + vqdmulh.s32 d16, d17 + vqdmulh.s16 q8, q9 + vqdmulh.s32 q8, q9 vqdmulh.s16 d11, d2, d3[0] @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] @ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] @ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] @ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x43,0xbc,0x92,0xf2] |