diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 7 |
2 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 301905b036..d87528ad5f 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -219,6 +219,8 @@ let Uses = [SP_64] in def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, Requires<[IsN64]>; +def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; + def DEXT : ExtBase<3, "dext", CPU64Regs>; def DINS : InsBase<7, "dins", CPU64Regs>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 12abee5b6d..3fcbfffe79 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -614,8 +614,9 @@ class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>: } // Read Hardware -class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd), - "rdhwr\t$rt, $rd", [], IIAlu> { +class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> + : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), + "rdhwr\t$rt, $rd", [], IIAlu> { let rs = 0; let shamt = 0; } @@ -901,7 +902,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>; def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, Requires<[HasMips32]>; -def RDHWR : ReadHardware; +def RDHWR : ReadHardware<CPURegs, HWRegs>; def EXT : ExtBase<0, "ext", CPURegs>; def INS : InsBase<4, "ins", CPURegs>; |