diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 3 | ||||
| -rw-r--r-- | utils/TableGen/ARMDecoderEmitter.cpp | 4 |
3 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 9d09a65da4..cc4fcfc3c8 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1253,7 +1253,7 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in // The 'adr' mnemonic encodes differently if the label is before or after // the instruction. The {24-21} opcode bits are set by the fixup, as we don't // know until then which form of the instruction will be used. -def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label), +def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> { bits<4> Rd; bits<12> label; diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 93d6a03005..16e6981382 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,5 +1,8 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# CHECK: addpl r4, pc, #19, 8 +0x4c 0x45 0x8f 0x52 + # CHECK: b #0 0x00 0x00 0x00 0xea diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index 09243e116b..b174fa961a 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1584,6 +1584,10 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "MOVr_TC") return false; + // Delegate ADR disassembly to the more generic ADDri/SUBri instructions. + if (Name == "ADR") + return false; + // // The following special cases are for conflict resolutions. // |