diff options
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMNaClRewritePass.cpp | 5 |
2 files changed, 12 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 56cfcface4..eb05665579 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -946,12 +946,14 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, TransferImpOps(MI, MIB, MIB); } else { // Inline version for native client. - // See native_client/src/untrusted/stubs/aeabi_read_tp.S - // mov r0, r9 - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), - ARM::R0) - .addReg(ARM::R9)) - .addReg(0); // Doesn't use/modify CPSR. + // See native_client/src/untrusted/nacl/aeabi_read_tp.S + // .nexe builds use this version, while irt builds use a call to + // __aeabi_read_tp. + // ldr r0, [r9, #0] + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::LDRi12), ARM::R0) + .addReg(ARM::R9) + .addImm(0)); } // @LOCALMOD-END MI.eraseFromParent(); diff --git a/lib/Target/ARM/ARMNaClRewritePass.cpp b/lib/Target/ARM/ARMNaClRewritePass.cpp index 91087aaaa2..d38cc8886c 100644 --- a/lib/Target/ARM/ARMNaClRewritePass.cpp +++ b/lib/Target/ARM/ARMNaClRewritePass.cpp @@ -531,7 +531,10 @@ void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB, bool IsLoad) { MachineOperand &Addr = MI.getOperand(AddrIdx); - if (!CPSRLive && TryPredicating(MI, ARMCC::EQ)) { + if (Addr.getReg() == ARM::R9) { + // R9-relative loads are no longer sandboxed. + assert(IsLoad && "There should be no r9-relative stores"); + } else if (!CPSRLive && TryPredicating(MI, ARMCC::EQ)) { /* * For unconditional memory references where CPSR is not in use, we can use * a faster sandboxing sequence by predicating the load/store -- assuming we |