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-rw-r--r--include/llvm/CodeGen/Analysis.h4
-rw-r--r--include/llvm/Support/TargetRegistry.h10
-rw-r--r--include/llvm/Target/Target.td2
-rw-r--r--include/llvm/Target/TargetMachine.h17
-rw-r--r--include/llvm/Target/TargetOptions.h278
-rw-r--r--lib/CodeGen/Analysis.cpp62
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfDebug.cpp2
-rw-r--r--lib/CodeGen/LLVMTargetMachine.cpp20
-rw-r--r--lib/CodeGen/PrologEpilogInserter.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp79
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp20
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp6
-rw-r--r--lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp2
-rw-r--r--lib/ExecutionEngine/JIT/JITEmitter.cpp14
-rw-r--r--lib/ExecutionEngine/TargetSelect.cpp2
-rw-r--r--lib/Target/ARM/ARMAsmPrinter.cpp7
-rw-r--r--lib/Target/ARM/ARMBaseRegisterInfo.cpp4
-rw-r--r--lib/Target/ARM/ARMFastISel.cpp2
-rw-r--r--lib/Target/ARM/ARMFrameLowering.cpp3
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp23
-rw-r--r--lib/Target/ARM/ARMTargetMachine.cpp14
-rw-r--r--lib/Target/ARM/ARMTargetMachine.h3
-rw-r--r--lib/Target/CBackend/CTargetMachine.h4
-rw-r--r--lib/Target/CellSPU/SPUFrameLowering.cpp3
-rw-r--r--lib/Target/CellSPU/SPUTargetMachine.cpp3
-rw-r--r--lib/Target/CellSPU/SPUTargetMachine.h2
-rw-r--r--lib/Target/CppBackend/CPPTargetMachine.h4
-rw-r--r--lib/Target/MBlaze/MBlazeFrameLowering.cpp3
-rw-r--r--lib/Target/MBlaze/MBlazeTargetMachine.cpp18
-rw-r--r--lib/Target/MBlaze/MBlazeTargetMachine.h1
-rw-r--r--lib/Target/MSP430/MSP430FrameLowering.cpp2
-rw-r--r--lib/Target/MSP430/MSP430TargetMachine.cpp3
-rw-r--r--lib/Target/MSP430/MSP430TargetMachine.h2
-rw-r--r--lib/Target/Mips/MipsFrameLowering.cpp4
-rw-r--r--lib/Target/Mips/MipsTargetMachine.cpp53
-rw-r--r--lib/Target/Mips/MipsTargetMachine.h8
-rw-r--r--lib/Target/PTX/PTXTargetMachine.cpp24
-rw-r--r--lib/Target/PTX/PTXTargetMachine.h6
-rw-r--r--lib/Target/PowerPC/PPCFrameLowering.cpp14
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp26
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td2
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp3
-rw-r--r--lib/Target/PowerPC/PPCTargetMachine.cpp11
-rw-r--r--lib/Target/PowerPC/PPCTargetMachine.h6
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.cpp15
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.h6
-rw-r--r--lib/Target/TargetLoweringObjectFile.cpp6
-rw-r--r--lib/Target/TargetMachine.cpp213
-rw-r--r--lib/Target/X86/X86FastISel.cpp6
-rw-r--r--lib/Target/X86/X86FrameLowering.cpp10
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp86
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp2
-rw-r--r--lib/Target/X86/X86Subtarget.cpp3
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp18
-rw-r--r--lib/Target/X86/X86TargetMachine.h6
-rw-r--r--lib/Target/XCore/XCoreFrameLowering.cpp3
-rw-r--r--lib/Target/XCore/XCoreTargetMachine.cpp3
-rw-r--r--lib/Target/XCore/XCoreTargetMachine.h2
-rw-r--r--tools/llc/llc.cpp158
-rw-r--r--tools/lto/LTOCodeGenerator.cpp3
-rw-r--r--tools/lto/LTOModule.cpp4
62 files changed, 728 insertions, 602 deletions
diff --git a/include/llvm/CodeGen/Analysis.h b/include/llvm/CodeGen/Analysis.h
index d8e64071a1..fda801cb97 100644
--- a/include/llvm/CodeGen/Analysis.h
+++ b/include/llvm/CodeGen/Analysis.h
@@ -70,6 +70,10 @@ bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
///
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
+/// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
+/// return the equivalent code if we're allowed to assume that NaNs won't occur.
+ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
+
/// getICmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR integer condition code.
///
diff --git a/include/llvm/Support/TargetRegistry.h b/include/llvm/Support/TargetRegistry.h
index e1ef39e5c6..ea55c91841 100644
--- a/include/llvm/Support/TargetRegistry.h
+++ b/include/llvm/Support/TargetRegistry.h
@@ -44,6 +44,7 @@ namespace llvm {
class MCTargetAsmLexer;
class MCTargetAsmParser;
class TargetMachine;
+ class TargetOptions;
class raw_ostream;
class formatted_raw_ostream;
@@ -86,6 +87,7 @@ namespace llvm {
StringRef TT,
StringRef CPU,
StringRef Features,
+ const TargetOptions &Options,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL);
@@ -334,13 +336,14 @@ namespace llvm {
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
- StringRef Features,
+ StringRef Features, const TargetOptions &Options,
Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default,
CodeGenOpt::Level OL = CodeGenOpt::Default) const {
if (!TargetMachineCtorFn)
return 0;
- return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM, OL);
+ return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
+ RM, CM, OL);
}
/// createMCAsmBackend - Create a target specific assembly parser.
@@ -1017,10 +1020,11 @@ namespace llvm {
private:
static TargetMachine *Allocator(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
- return new TargetMachineImpl(T, TT, CPU, FS, RM, CM, OL);
+ return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
}
};
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 9714172aa4..8582015e77 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -423,7 +423,7 @@ class Predicate<string cond> {
/// NoHonorSignDependentRounding - This predicate is true if support for
/// sign-dependent-rounding is not enabled.
def NoHonorSignDependentRounding
- : Predicate<"!HonorSignDependentRoundingFPMath()">;
+ : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
class Requires<list<Predicate> preds> {
list<Predicate> Predicates = preds;
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 4a5f33e401..c169e063d0 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -14,6 +14,7 @@
#ifndef LLVM_TARGET_TARGETMACHINE_H
#define LLVM_TARGET_TARGETMACHINE_H
+#include "llvm/Target/TargetOptions.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/ADT/StringRef.h"
#include <cassert>
@@ -63,7 +64,7 @@ class TargetMachine {
void operator=(const TargetMachine &); // DO NOT IMPLEMENT
protected: // Can only create subclasses.
TargetMachine(const Target &T, StringRef TargetTriple,
- StringRef CPU, StringRef FS);
+ StringRef CPU, StringRef FS, const TargetOptions &Options);
/// getSubtargetImpl - virtual method implemented by subclasses that returns
/// a reference to that target's TargetSubtargetInfo-derived member variable.
@@ -101,6 +102,8 @@ public:
const StringRef getTargetCPU() const { return TargetCPU; }
const StringRef getTargetFeatureString() const { return TargetFS; }
+ TargetOptions Options;
+
// Interfaces to the major aspects of target machine information:
// -- Instruction opcode and operand information
// -- Pipelines and scheduling information
@@ -284,10 +287,20 @@ public:
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
- StringRef CPU, StringRef FS,
+ StringRef CPU, StringRef FS, TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
+ /// printNoVerify - Add a pass to dump the machine function, if debugging is
+ /// enabled.
+ ///
+ void printNoVerify(PassManagerBase &PM, const char *Banner) const;
+
+ /// printAndVerify - Add a pass to dump then verify the machine function, if
+ /// those steps are enabled.
+ ///
+ void printAndVerify(PassManagerBase &PM, const char *Banner) const;
+
private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index 36913413b7..30018163aa 100644
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -15,6 +15,8 @@
#ifndef LLVM_TARGET_TARGETOPTIONS_H
#define LLVM_TARGET_TARGETOPTIONS_H
+#include <string>
+
namespace llvm {
class MachineFunction;
class StringRef;
@@ -27,140 +29,156 @@ namespace llvm {
Hard // Hard float.
};
}
-
- /// PrintMachineCode - This flag is enabled when the -print-machineinstrs
- /// option is specified on the command line, and should enable debugging
- /// output from the code generator.
- extern bool PrintMachineCode;
-
- /// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
- /// specified on the command line. If the target supports the frame pointer
- /// elimination optimization, this option should disable it.
- extern bool NoFramePointerElim;
-
- /// NoFramePointerElimNonLeaf - This flag is enabled when the
- /// -disable-non-leaf-fp-elim is specified on the command line. If the target
- /// supports the frame pointer elimination optimization, this option should
- /// disable it for non-leaf functions.
- extern bool NoFramePointerElimNonLeaf;
-
- /// DisableFramePointerElim - This returns true if frame pointer elimination
- /// optimization should be disabled for the given machine function.
- extern bool DisableFramePointerElim(const MachineFunction &MF);
-
- /// LessPreciseFPMAD - This flag is enabled when the
- /// -enable-fp-mad is specified on the command line. When this flag is off
- /// (the default), the code generator is not allowed to generate mad
- /// (multiply add) if the result is "less precise" than doing those operations
- /// individually.
- extern bool LessPreciseFPMADOption;
- extern bool LessPreciseFPMAD();
-
- /// NoExcessFPPrecision - This flag is enabled when the
- /// -disable-excess-fp-precision flag is specified on the command line. When
- /// this flag is off (the default), the code generator is allowed to produce
- /// results that are "more precise" than IEEE allows. This includes use of
- /// FMA-like operations and use of the X86 FP registers without rounding all
- /// over the place.
- extern bool NoExcessFPPrecision;
-
- /// UnsafeFPMath - This flag is enabled when the
- /// -enable-unsafe-fp-math flag is specified on the command line. When
- /// this flag is off (the default), the code generator is not allowed to
- /// produce results that are "less precise" than IEEE allows. This includes
- /// use of X86 instructions like FSIN and FCOS instead of libcalls.
- /// UnsafeFPMath implies LessPreciseFPMAD.
- extern bool UnsafeFPMath;
-
- /// NoInfsFPMath - This flag is enabled when the
- /// -enable-no-infs-fp-math flag is specified on the command line. When
- /// this flag is off (the default), the code generator is not allowed to
- /// assume the FP arithmetic arguments and results are never +-Infs.
- extern bool NoInfsFPMath;
-
- /// NoNaNsFPMath - This flag is enabled when the
- /// -enable-no-nans-fp-math flag is specified on the command line. When
- /// this flag is off (the default), the code generator is not allowed to
- /// assume the FP arithmetic arguments and results are never NaNs.
- extern bool NoNaNsFPMath;
-
- /// HonorSignDependentRoundingFPMath - This returns true when the
- /// -enable-sign-dependent-rounding-fp-math is specified. If this returns
- /// false (the default), the code generator is allowed to assume that the
- /// rounding behavior is the default (round-to-zero for all floating point to
- /// integer conversions, and round-to-nearest for all other arithmetic
- /// truncations). If this is enabled (set to true), the code generator must
- /// assume that the rounding mode may dynamically change.
- extern bool HonorSignDependentRoundingFPMathOption;
- extern bool HonorSignDependentRoundingFPMath();
-
- /// UseSoftFloat - This flag is enabled when the -soft-float flag is specified
- /// on the command line. When this flag is on, the code generator will
- /// generate libcalls to the software floating point library instead of
- /// target FP instructions.
- extern bool UseSoftFloat;
-
- /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
- /// on the command line. This setting may either be Default, Soft, or Hard.
- /// Default selects the target's default behavior. Soft selects the ABI for
- /// UseSoftFloat, but does not inidcate that FP hardware may not be used.
- /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
- /// Hard presumes that the normal FP ABI is used.
- extern FloatABI::ABIType FloatABIType;
-
- /// NoZerosInBSS - By default some codegens place zero-initialized data to
- /// .bss section. This flag disables such behaviour (necessary, e.g. for
- /// crt*.o compiling).
- extern bool NoZerosInBSS;
-
- /// JITExceptionHandling - This flag indicates that the JIT should emit
- /// exception handling information.
- extern bool JITExceptionHandling;
-
- /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit
- /// debug information and notify a debugger about it.
- extern bool JITEmitDebugInfo;
-
- /// JITEmitDebugInfoToDisk - This flag indicates that the JIT should write
- /// the object files generated by the JITEmitDebugInfo flag to disk. This
- /// flag is hidden and is only for debugging the debug info.
- extern bool JITEmitDebugInfoToDisk;
-
- /// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
- /// specified on the commandline. When the flag is on, participating targets
- /// will perform tail call optimization on all calls which use the fastcc
- /// calling convention and which satisfy certain target-independent
- /// criteria (being at the end of a function, having the same return type
- /// as their parent function, etc.), using an alternate ABI if necessary.
- extern bool GuaranteedTailCallOpt;
-
- /// StackAlignmentOverride - Override default stack alignment for target.
- extern unsigned StackAlignmentOverride;
-
- /// RealignStack - This flag indicates whether the stack should be
- /// automatically realigned, if needed.
- extern bool RealignStack;
-
- /// DisableJumpTables - This flag indicates jump tables should not be
- /// generated.
- extern bool DisableJumpTables;
-
- /// EnableFastISel - This flag enables fast-path instruction selection
- /// which trades away generated code quality in favor of reducing
- /// compile time.
- extern bool EnableFastISel;
-
+
/// StrongPHIElim - This flag enables more aggressive PHI elimination
/// wth earlier copy coalescing.
extern bool StrongPHIElim;
- /// getTrapFunctionName - If this returns a non-empty string, this means isel
- /// should lower Intrinsic::trap to a call to the specified function name
- /// instead of an ISD::TRAP node.
- extern StringRef getTrapFunctionName();
-
- extern bool EnableSegmentedStacks;
-
+ class TargetOptions {
+ public:
+ TargetOptions()
+ : PrintMachineCode(false), NoFramePointerElim(false),
+ NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false),
+ NoExcessFPPrecision(false), UnsafeFPMath(false), NoInfsFPMath(false),
+ NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false),
+ UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false),
+ JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
+ GuaranteedTailCallOpt(false), StackAlignmentOverride(0),
+ RealignStack(true), DisableJumpTables(false), EnableFastISel(false),
+ EnableSegmentedStacks(false), TrapFuncName(""),
+ FloatABIType(FloatABI::Default)
+ {}
+
+ /// PrintMachineCode - This flag is enabled when the -print-machineinstrs
+ /// option is specified on the command line, and should enable debugging
+ /// output from the code generator.
+ unsigned PrintMachineCode : 1;
+
+ /// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
+ /// specified on the command line. If the target supports the frame pointer
+ /// elimination optimization, this option should disable it.
+ unsigned NoFramePointerElim : 1;
+
+ /// NoFramePointerElimNonLeaf - This flag is enabled when the
+ /// -disable-non-leaf-fp-elim is specified on the command line. If the
+ /// target supports the frame pointer elimination optimization, this option
+ /// should disable it for non-leaf functions.
+ unsigned NoFramePointerElimNonLeaf : 1;
+
+ /// DisableFramePointerElim - This returns true if frame pointer elimination
+ /// optimization should be disabled for the given machine function.
+ bool DisableFramePointerElim(const MachineFunction &MF) const;
+
+ /// LessPreciseFPMAD - This flag is enabled when the
+ /// -enable-fp-mad is specified on the command line. When this flag is off
+ /// (the default), the code generator is not allowed to generate mad
+ /// (multiply add) if the result is "less precise" than doing those
+ /// operations individually.
+ unsigned LessPreciseFPMADOption : 1;
+ bool LessPreciseFPMAD() const;
+
+ /// NoExcessFPPrecision - This flag is enabled when the
+ /// -disable-excess-fp-precision flag is specified on the command line.
+ /// When this flag is off (the default), the code generator is allowed to
+ /// produce results that are "more precise" than IEEE allows. This includes
+ /// use of FMA-like operations and use of the X86 FP registers without
+ /// rounding all over the place.
+ unsigned NoExcessFPPrecision : 1;
+
+ /// UnsafeFPMath - This flag is enabled when the
+ /// -enable-unsafe-fp-math flag is specified on the command line. When
+ /// this flag is off (the default), the code generator is not allowed to
+ /// produce results that are "less precise" than IEEE allows. This includes
+ /// use of X86 instructions like FSIN and FCOS instead of libcalls.
+ /// UnsafeFPMath implies LessPreciseFPMAD.
+ unsigned UnsafeFPMath : 1;
+
+ /// NoInfsFPMath - This flag is enabled when the
+ /// -enable-no-infs-fp-math flag is specified on the command line. When
+ /// this flag is off (the default), the code generator is not allowed to
+ /// assume the FP arithmetic arguments and results are never +-Infs.
+ unsigned NoInfsFPMath : 1;
+
+ /// NoNaNsFPMath - This flag is enabled when the
+ /// -enable-no-nans-fp-math flag is specified on the command line. When
+ /// this flag is off (the default), the code generator is not allowed to
+ /// assume the FP arithmetic arguments and results are never NaNs.
+ unsigned NoNaNsFPMath : 1;
+
+ /// HonorSignDependentRoundingFPMath - This returns true when the
+ /// -enable-sign-dependent-rounding-fp-math is specified. If this returns
+ /// false (the default), the code generator is allowed to assume that the
+ /// rounding behavior is the default (round-to-zero for all floating point
+ /// to integer conversions, and round-to-nearest for all other arithmetic
+ /// truncations). If this is enabled (set to true), the code generator must
+ /// assume that the rounding mode may dynamically change.
+ unsigned HonorSignDependentRoundingFPMathOption : 1;
+ bool HonorSignDependentRoundingFPMath() const;
+
+ /// UseSoftFloat - This flag is enabled when the -soft-float flag is
+ /// specified on the command line. When this flag is on, the code generator
+ /// will generate libcalls to the software floating point library instead of
+ /// target FP instructions.
+ unsigned UseSoftFloat : 1;
+
+ /// NoZerosInBSS - By default some codegens place zero-initialized data to
+ /// .bss section. This flag disables such behaviour (necessary, e.g. for
+ /// crt*.o compiling).
+ unsigned NoZerosInBSS : 1;
+
+ /// JITExceptionHandling - This flag indicates that the JIT should emit
+ /// exception handling information.
+ unsigned JITExceptionHandling : 1;
+
+ /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit
+ /// debug information and notify a debugger about it.
+ unsigned JITEmitDebugInfo : 1;
+
+ /// JITEmitDebugInfoToDisk - This flag indicates that the JIT should write
+ /// the object files generated by the JITEmitDebugInfo flag to disk. This
+ /// flag is hidden and is only for debugging the debug info.
+ unsigned JITEmitDebugInfoToDisk : 1;
+
+ /// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
+ /// specified on the commandline. When the flag is on, participating targets
+ /// will perform tail call optimization on all calls which use the fastcc
+ /// calling convention and which satisfy certain target-independent
+ /// criteria (being at the end of a function, having the same return type
+ /// as their parent function, etc.), using an alternate ABI if necessary.
+ unsigned GuaranteedTailCallOpt : 1;
+
+ /// StackAlignmentOverride - Override default stack alignment for target.
+ unsigned StackAlignmentOverride;
+
+ /// RealignStack - This flag indicates whether the stack should be
+ /// automatically realigned, if needed.
+ unsigned RealignStack : 1;
+
+ /// DisableJumpTables - This flag indicates jump tables should not be
+ /// generated.
+ unsigned DisableJumpTables : 1;
+
+ /// EnableFastISel - This flag enables fast-path instruction selection
+ /// which trades away generated code quality in favor of reducing
+ /// compile time.
+ unsigned EnableFastISel : 1;
+
+ unsigned EnableSegmentedStacks : 1;
+
+ /// getTrapFunctionName - If this returns a non-empty string, this means
+ /// isel should lower Intrinsic::trap to a call to the specified function
+ /// name instead of an ISD::TRAP node.
+ std::string TrapFuncName;
+ StringRef getTrapFunctionName() const;
+
+ /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
+ /// on the command line. This setting may either be Default, Soft, or Hard.
+ /// Default selects the target's default behavior. Soft selects the ABI for
+ /// UseSoftFloat, but does not indicate that FP hardware may not be used.
+ /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
+ /// Hard presumes that the normal FP ABI is used.
+ FloatABI::ABIType FloatABIType;
+ };
} // End llvm namespace
#endif
diff --git a/lib/CodeGen/Analysis.cpp b/lib/CodeGen/Analysis.cpp
index fafc01044d..fc28b21194 100644
--- a/lib/CodeGen/Analysis.cpp
+++ b/lib/CodeGen/Analysis.cpp
@@ -1,4 +1,4 @@
-//===-- Analysis.cpp - CodeGen LLVM IR Analysis Utilities --*- C++ ------*-===//
+//===-- Analysis.cpp - CodeGen LLVM IR Analysis Utilities -----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -149,33 +149,40 @@ llvm::hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
/// consideration of global floating-point math flags.
///
ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
- ISD::CondCode FPC, FOC;
switch (Pred) {
- case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
- case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
- case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
- case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
- case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
- case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
- case FCmpInst::FCMP_ONE: