diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/ARM/smml.ll | 13 |
2 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index e89c2312fe..f506a296de 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3554,8 +3554,7 @@ def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), - IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", - [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>, + IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, Requires<[IsARM, HasV6]>; def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), diff --git a/test/CodeGen/ARM/smml.ll b/test/CodeGen/ARM/smml.ll new file mode 100644 index 0000000000..99df0d4c96 --- /dev/null +++ b/test/CodeGen/ARM/smml.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp { +entry: +; CHECK-NOT: smmls + %conv4 = zext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %conv2 = sext i32 %c to i64 + %mul = mul nsw i64 %conv2, %conv1 + %shr5 = lshr i64 %mul, 32 + %sub = sub nsw i64 %conv4, %shr5 + %conv3 = trunc i64 %sub to i32 + ret i32 %conv3 +} |